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51.发明授权公开(公告)号：US08433018B2
公开(公告)日：2013-04-30
申请号：US12130732
申请日：2008-05-30
IPC分类号： H04L7/00
CPC分类号： H03L7/0893 , H03K5/133 , H03K2005/00052 , H03L7/081 , H03L7/0895 , H03L7/093 , H03L7/0998 , H03L7/18
摘要： A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.
摘要翻译： 频率合成电路包括锁相环和内插器电路。 锁相环电路接收参考时钟和反馈时钟，并产生基于参考时钟和反馈时钟的频率的输出时钟。 内插器电路耦合在锁相环电路的反馈路径中。 内插器控制电路产生指定内插器电路的可变时间延迟的内插器控制字。 内插器电路接收输出时钟，并根据内插器控制字在输出时钟中引入可变时间延迟来产生反馈时钟。 时间可变延迟会改变输出电路的频率。 公开了包括扩频频率时钟发生器，频率调制器和固定频率时钟发生器电路的频率合成电路的实施例。
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公开(公告)号：US07724815B1
公开(公告)日：2010-05-25
申请号：US11711520
申请日：2007-02-27
申请人： Prasun K. Raha , Dean Liu
发明人： Prasun K. Raha , Dean Liu
CPC分类号： H03H7/38 , H03H7/46 , H04L25/0298
摘要： A method and apparatus for a receive equalizer of a gigabit transceiver that is reconfigurable to support multiple communication standards. Communication standards having variable common mode and coupling requirements are accommodated through the use of reconfigurable integrated circuits (ICs), such as field programmable gate arrays (FPGAs), that provide a plurality of reconfigurable transceivers that are programmable through configuration, or partial reconfiguration, events. The reconfigurable transceivers apply internally generated common mode voltage signals to the differential input in support of the various communication standards.
摘要翻译： 用于千兆位收发器的接收均衡器的方法和装置，其可重新配置以支持多种通信标准。 通过使用诸如现场可编程门阵列（FPGA）的可重构集成电路（IC）来提供具有可变共模和耦合要求的通信标准，其提供可通过配置或部分重配置事件来编程的多个可重新配置的收发器 。 可重新配置的收发器将内部生成的共模电压信号应用于差分输入，以支持各种通信标准。
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53.发明授权公开(公告)号：US07432750B1
公开(公告)日：2008-10-07
申请号：US11296786
申请日：2005-12-07
CPC分类号： H03L7/0893 , H03K5/133 , H03K2005/00052 , H03L7/081 , H03L7/0895 , H03L7/093 , H03L7/0998 , H03L7/18
摘要： A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.
摘要翻译： 频率合成电路包括锁相环和内插器电路。 锁相环电路接收参考时钟和反馈时钟，并产生基于参考时钟和反馈时钟的频率的输出时钟。 内插器电路耦合在锁相环电路的反馈路径中。 内插器控制电路产生指定内插器电路的可变时间延迟的内插器控制字。 内插器电路接收输出时钟，并根据内插器控制字在输出时钟中引入可变时间延迟来产生反馈时钟。 时间可变延迟会改变输出电路的频率。 公开了包括扩频频率时钟发生器，频率调制器和固定频率时钟发生器电路的频率合成电路的实施例。
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公开(公告)号：US06618277B2
公开(公告)日：2003-09-09
申请号：US09930537
申请日：2001-08-14
IPC分类号： H02M700
摘要： An apparatus for reducing power supply noise in the power supply system of a clock driver has been developed. The apparatus includes a clock driver with a power supply system connected to the clock driver and a shunting resistor connected across the power supply system in parallel with the clock driver.
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55.发明授权Delay locked loop design with switch for loop filter capacitance leakage current control 有权延迟锁定环路设计，带开关用于环路滤波器电容漏电流控制公开(公告)号：US06597219B1
公开(公告)日：2003-07-22
申请号：US10199422
申请日：2002-07-19
申请人： Pradeep Trivedi , Claude R. Gauthier , Dean Liu
发明人： Pradeep Trivedi , Claude R. Gauthier , Dean Liu
IPC分类号： H03L706
CPC分类号： H03L7/0891 , H03L7/0812
摘要： A delay locked loop design that uses a switch operatively connected to a loop filter capacitor to control a leakage current of the loop filter capacitor is provided. By positioning a switch in series with the loop filter capacitor, the leakage current of the loop filter capacitor may be controlled by switching the switch ‘on’ when a charge pump of the delay locked loop is ‘on’ and switching the switch ‘off’ when the charge pump is ‘off,’ thereby cumulatively reducing the leakage current of the loop filter capacitor throughput the operation of the delay locked loop. Control and reduction of the loop filter capacitor leakage current leads to more reliable and stable delay locked loop behavior.
摘要翻译： 提供了延迟锁定环设计，其使用可操作地连接到环路滤波电容器的开关来控制环路滤波电容器的漏电流。 通过将开关与环路滤波电容器串联定位，可以通过在延迟锁定环路的电荷泵“开”时切换开关“开”来控制环路滤波电容器的漏电流，并将开关“关闭” 当电荷泵“关闭”时，累积减少环路滤波电容器漏电流的吞吐量延迟锁定环路的运行。 控制和减少环路滤波电容器的漏电流导致更可靠和稳定的延迟锁定环行为。
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公开(公告)号：US06495926B1
公开(公告)日：2002-12-17
申请号：US09997471
申请日：2001-11-29
申请人： Sudhakar Bobba , Tyler Thorp , Dean Liu
发明人： Sudhakar Bobba , Tyler Thorp , Dean Liu
IPC分类号： H01L2348
CPC分类号： H01L24/17 , H01L23/50 , H01L23/5286 , H01L2224/13099 , H01L2924/00014 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2224/0401
摘要： A 60 degree bump placement layout for an integrated circuit power grid is provided. This layout improves integrated circuit performance and reliability and gives an integrated circuit designer added flexibility and uniformity in designing the integrated circuit. Further, a patterned bump array for a top metal layer of an integrated circuit having a plurality of 60 degree bump placement structures is provided.
摘要翻译： 提供集成电路电网的60度凸块布置布局。 这种布局提高了集成电路的性能和可靠性，并为集成电路设计人员增加了设计集成电路的灵活性和均匀性。 此外，提供了具有多个60度凸块放置结构的集成电路的顶部金属层的图案化凸块阵列。
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公开(公告)号：US06476663B1
公开(公告)日：2002-11-05
申请号：US09929151
申请日：2001-08-14
IPC分类号： H01L3500
CPC分类号： G01K7/00 , H01L23/34 , H01L2924/0002 , H01L2924/00
摘要： A method for reducing power supply noise in the power supply system of a thermal sensor has been developed. The method includes powering up a thermal sensor and inserting a shunting resistance across the power supply terminals. The shunting resistance is inserted in parallel with the thermal sensor.
摘要翻译： 已经开发了用于降低热传感器的电源系统中的电源噪声的方法。 该方法包括加热热传感器并在电源端子上插入分流电阻。 分流电阻与热传感器并联插入。
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公开(公告)号：US6021298A
公开(公告)日：2000-02-01
申请号：US237764
申请日：1999-01-26
IPC分类号： G03G15/08
CPC分类号： G03G15/0812
摘要： The doctor blade arrangement described in the specification includes a doctor blade made of resilient sheet material having a toner thickness control end lightly engaging a toner layer on the surface of a development roller to control the thickness of the toner layer and a mounting end which is bent to be resiliently received in a mounting groove of the electrophotographic apparatus in which doctor blade is used. In one embodiment the mounting end has parallel bends forming a U-shape leading to a projecting mounting lip which is engaged by a projecting hook portion at one edge of the mounting groove. In other embodiments the mounting lip extends toward or away from the plane of the toner thickness control end of the doctor blade.
摘要翻译： 在说明书中描述的刮刀装置包括由弹性片材制成的刮刀，其具有调色剂厚度控制端，其轻微地接合显影辊表面上的调色剂层，以控制调色剂层的厚度和弯曲的安装端 被弹性地容纳在使用刮刀的电子照相设备的安装槽中。 在一个实施例中，安装端具有形成U形的平行弯曲部，其形成为突出的安装唇缘，凸出的安装唇缘由安装槽的一个边缘处的突出的钩部接合。 在其它实施例中，安装唇朝向或远离刮刀的调色剂厚度控制端的平面延伸。
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