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    Method and apparatus for a mesochronous transmission system
    1.
    发明授权
    Method and apparatus for a mesochronous transmission system 有权
    中间传输系统的方法和装置

    公开(公告)号：US07978802B1

    公开(公告)日：2011-07-12

    申请号：US11974362

    申请日：2007-10-12

    申请人： Prasun K. Raha ,  Donald Stark ,  Dean Liu ,  Pak Shing Chau

    发明人： Prasun K. Raha ,  Donald Stark ,  Dean Liu ,  Pak Shing Chau

    IPC分类号： H04L7/00

    CPC分类号： H04L7/0025 ,  H03L7/07 ,  H03L7/081 ,  H03L7/0814 ,  H03L7/087 ,  H04L7/0331

    摘要： A method and apparatus for a multiple lane transmission system that provides both a low latency mode of operation, while at the same time, provides reduced lane-lane skew. The overall transmission system operates as a mesochronous system, whereby each clock domain of the transmission system is synchronized to the leaf nodes of a global clock tree. A phase aligner is then used to align the phase of both the bit and byte clocks of each transmission lane to the clock signal generated at the leaf nodes of the global clock tree.

    摘要翻译： 一种用于多通道传输系统的方法和装置，其提供低等待时间操作模式，同时提供减少的车道歪斜。 整个传输系统作为中间同步系统工作，由此传输系统的每个时钟域与全局时钟树的叶节点同步。 然后使用相位对准器将每个传输通道的位和字节时钟的相位与在全局时钟树的叶节点处生成的时钟信号进行对准。

    Method and apparatus for a programmably terminated receiver
    2.
    发明授权
    Method and apparatus for a programmably terminated receiver 有权
    用于可编程终止的接收机的方法和装置

    公开(公告)号：US07724815B1

    公开(公告)日：2010-05-25

    申请号：US11711520

    申请日：2007-02-27

    申请人： Prasun K. Raha ,  Dean Liu

    发明人： Prasun K. Raha ,  Dean Liu

    IPC分类号： H03H7/30 ,  H03H7/40 ,  H03K5/159

    CPC分类号： H03H7/38 ,  H03H7/46 ,  H04L25/0298

    摘要： A method and apparatus for a receive equalizer of a gigabit transceiver that is reconfigurable to support multiple communication standards. Communication standards having variable common mode and coupling requirements are accommodated through the use of reconfigurable integrated circuits (ICs), such as field programmable gate arrays (FPGAs), that provide a plurality of reconfigurable transceivers that are programmable through configuration, or partial reconfiguration, events. The reconfigurable transceivers apply internally generated common mode voltage signals to the differential input in support of the various communication standards.

    摘要翻译： 用于千兆位收发器的接收均衡器的方法和装置，其可重新配置以支持多种通信标准。 通过使用诸如现场可编程门阵列（FPGA）的可重构集成电路（IC）来提供具有可变共模和耦合要求的通信标准，其提供可通过配置或部分重配置事件来编程的多个可重新配置的收发器 。 可重新配置的收发器将内部生成的共模电压信号应用于差分输入，以支持各种通信标准。

    Frequency and phase correction in a phase-locked loop (PLL)
    5.
    发明授权
    Frequency and phase correction in a phase-locked loop (PLL) 有权
    锁相环（PLL）中的频率和相位校正

    公开(公告)号：US07277519B2

    公开(公告)日：2007-10-02

    申请号：US10725763

    申请日：2003-12-02

    申请人： Prasun K. Raha ,  T. Lakshmi Viswanathan ,  Richard E. Jennings

    发明人： Prasun K. Raha ,  T. Lakshmi Viswanathan ,  Richard E. Jennings

    IPC分类号： H03D3/24

    CPC分类号： H03L7/107 ,  H03L7/0893 ,  H03L7/093 ,  H03L7/0995 ,  H03L7/1072

    摘要： In one embodiment, a system for frequency and phase correction in a phase-locked loop (PLL) includes a phase frequency detector, first and second charge pumps respectively generating a first current and a voltage, a voltage-to-current (V2I) converter, a current summer, and a current-controlled oscillator (CCO). The phase frequency detector detects a frequency difference and a phase difference between a clock signal and a comparison signal, communicates the frequency difference to a first charge pump generating a first current, and communicates the phase difference to a second charge pump generating a voltage. The comparison signal is derived from an output signal of the PLL. The first charge pump modifies the first current according to the frequency difference and communicates the first current to the current summer. The second charge pump modifies the voltage according to the phase difference and communicates the voltage to the V2I converter. The V2I converter generates a second current corresponding to the voltage and communicates the second current to the current summer. The current summer combines the first and second currents with each other to generate a control current for the CCO and communicates the control current to the CCO. The CCO generates one or more oscillating signals according to the first and second currents. A frequency of an oscillating signal from the CCO changes in response to the modification of the first current, and a phase of the oscillating signal changes in response to the modification of the second current.

    摘要翻译： 在一个实施例中，用于锁相环（PLL）中的频率和相位校正的系统包括相位频率检测器，分别产生第一电流和电压的第一和第二电荷泵，电压 - 电流（V2I）转换器 ，当前夏天和电流控制振荡器（CCO）。 相位频率检测器检测时钟信号和比较信号之间的频率差和相位差，将频差传送到产生第一电流的第一电荷泵，并将相位差传送到产生电压的第二电荷泵。 比较信号从PLL的输出信号导出。 第一个电荷泵根据频差改变第一个电流，并将第一个电流传送到当前夏天。 第二个电荷泵根据相位差修改电压，并将电压传递给V2I转换器。 V2I转换器产生对应于电压的第二电流，并将第二电流传送到当前夏天。 当前的夏天将第一和第二电流彼此相结合，以产生CCO的控制电流，并将控制电流传递给CCO。 CCO根据第一和第二电流产生一个或多个振荡信号。 来自CCO的振荡信号的频率响应于第一电流的修改而改变，并且振荡信号的相位响应于第二电流的修改而改变。

    Load sensing voltage regulator for PLL/DLL architectures
    6.
    发明授权
    Load sensing voltage regulator for PLL/DLL architectures 有权
    负载感应电压调节器用于PLL / DLL架构

    公开(公告)号：US06940337B2

    公开(公告)日：2005-09-06

    申请号：US10749275

    申请日：2003-12-29

    申请人： T. Lakshmi Viswanathan ,  Prasun K. Raha

    发明人： T. Lakshmi Viswanathan ,  Prasun K. Raha

    IPC分类号： G05F1/10 ,  G05F1/46

    CPC分类号： G05F1/465

    摘要： An apparatus includes a voltage regulator operable to regulate a supply voltage to an on-chip module having an operational current, draw a supply current, and supply the operation current to the on-chip module. The supply current drawn by the voltage regulator is proportional to the operating current of the on-chip module.

    摘要翻译： 一种装置包括电压调节器，其可操作以调节具有工作电流的片上模块的电源电压，绘制电源电流，并将操作电流提供给片上模块。 电压调节器提供的电源电流与片上模块的工作电流成比例。