公开(公告)号：US08258057B2

公开(公告)日：2012-09-04

申请号：US11396201

申请日：2006-05-23

申请人： Kelin J. Kuhn ,  Kaizad Mistry ,  Mark Bohr ,  Chris Auth

发明人： Kelin J. Kuhn ,  Kaizad Mistry ,  Mark Bohr ,  Chris Auth

IPC分类号： H01L21/4763

CPC分类号： H01L29/41725 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76859 ,  H01L21/76874 ,  H01L23/485 ,  H01L23/5226 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of fabricating a first contact to a semiconductor device, which fundamentally comprises providing a semiconductor device formed on a substrate. The substrate further includes a conductive surface. A dielectric layer is formed over the substrate and has an opening exposing the conductive surface. The opening extends an entire length of the semiconductor device, partway down the entire length of the device, extending from the device onto adjacent field of the device, or and a combination thereof. A barrier layer is formed within the opening. A copper containing material fills the opening to form a first contact to the semiconductor device.

摘要翻译： 制造半导体器件的第一接触的方法，其基本上包括提供形成在衬底上的半导体器件。 基板还包括导电表面。 介电层形成在衬底上并具有暴露导电表面的开口。 开口延伸半导体器件的整个长度，从设备的整个长度的一部分延伸到器件的相邻的场上，或其组合。 在开口内形成阻挡层。 含铜材料填充开口以形成与半导体器件的第一接触。

公开(公告)号：US06627506B2

公开(公告)日：2003-09-30

申请号：US09908277

申请日：2001-07-18

申请人： Kelin J. Kuhn ,  Ian R. Post

发明人： Kelin J. Kuhn ,  Ian R. Post

IPC分类号： H01L21331

CPC分类号： H01L21/3144 ,  H01L21/76232

摘要： The present invention relates to a method of forming an isolation trench that comprises forming a recess in a substrate and forming a film upon the sidewall under conditions that cause the film to have a tensile load. The method includes filling the recess with a material that imparts a compressive load upon the film under conditions that oppose the tensile load. The present invention is particularly well suited for shallow isolation trench filling in the 0.13 micron geometry range, and smaller.

公开(公告)号：US20140264879A1

公开(公告)日：2014-09-18

申请号：US14289581

申请日：2014-05-28

申请人： Kelin J. Kuhn ,  Kaizad Mistry ,  Mark Bohr ,  Chris Auth

发明人： Kelin J. Kuhn ,  Kaizad Mistry ,  Mark Bohr ,  Chris Auth

IPC分类号： H01L29/45

CPC分类号： H01L29/41725 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76859 ,  H01L21/76874 ,  H01L23/485 ,  H01L23/5226 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of fabricating a first contact to a semiconductor device, which fundamentally comprises providing a semiconductor device formed on a substrate. The substrate further includes a conductive surface. A dielectric layer is formed over the substrate and has an opening exposing the conductive surface. The opening extends an entire length of the semiconductor device, partway down the entire length of the device, extending from the device onto adjacent field of the device, or and a combination thereof. A barrier layer is formed within the opening. A copper containing material fills the opening to form a first contact to the semiconductor device.

摘要翻译： 制造半导体器件的第一接触的方法，其基本上包括提供形成在衬底上的半导体器件。 基板还包括导电表面。 介电层形成在衬底上并具有暴露导电表面的开口。 开口延伸半导体器件的整个长度，从设备的整个长度的一部分延伸到器件的相邻的场上，或其组合。 在开口内形成阻挡层。 含铜材料填充开口以形成与半导体器件的第一接触。

公开(公告)号：US09484447B2

公开(公告)日：2016-11-01

申请号：US13539195

申请日：2012-06-29

申请人： Seiyon Kim ,  Kelin J. Kuhn ,  Tahir Ghani ,  Anand S. Murthy ,  Mark Armstrong ,  Rafael Rios ,  Abhijit Jayant Pethe ,  Willy Rachmady

发明人： Seiyon Kim ,  Kelin J. Kuhn ,  Tahir Ghani ,  Anand S. Murthy ,  Mark Armstrong ,  Rafael Rios ,  Abhijit Jayant Pethe ,  Willy Rachmady

IPC分类号： H01L29/78 ,  H01L21/336 ,  B82Y40/00 ,  B82Y99/00 ,  H01L29/06 ,  H01L29/786

CPC分类号： H01L29/0673 ,  B82Y40/00 ,  H01L21/30604 ,  H01L21/3105 ,  H01L21/31155 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78 ,  H01L29/78696

摘要： A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

摘要翻译： 公开了一种具有多个内部间隔物的纳米线器件和用于形成所述内部间隔物的方法。 在一个实施例中，半导体器件包括设置在衬底上方的纳米线堆叠，纳米线堆叠具有多个垂直堆叠的纳米线，围绕多个纳米线中的每一个缠绕的栅极结构，限定器件的沟道区，栅极 结构，其具有栅极侧壁，在沟道区域的相对侧上的一对源极/漏极区域; 以及位于纳米线堆叠内部的两个相邻纳米线之间的栅极侧壁的一部分上的内部间隔物。 在一个实施例中，内部间隔物通过在与沟道区相邻蚀刻的凹坑中沉积间隔物形成。 在一个实施例中，通过沟道区蚀刻凹坑。 在另一个实施例中，通过源/漏区蚀刻凹坑。

公开(公告)号：US20150179786A1

公开(公告)日：2015-06-25

申请号：US14138254

申请日：2013-12-23

申请人： Seiyon Kim ,  Kelin J. Kuhn

发明人： Seiyon Kim ,  Kelin J. Kuhn

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/41 ,  H01L29/66 ,  H01L29/51

CPC分类号： H01L29/785 ,  H01L21/565 ,  H01L29/66795

摘要： An embodiment concerns selective etching of a structure (e.g., a fin) to form a void with the shape of the original structure. This void then functions as a mold. Flowable dielectric material fills the void to form the same shape as the original structure/mold. Post-processing then occurs (e.g., oxidation build up and annealing) to harden the dielectric in the void. The resulting product is a molded dielectric nanostructure that has the same shape as the original structure but consists of a different material (e.g., dielectric instead of silicon). Other embodiments are described herein.

摘要翻译： 实施例涉及对结构（例如，翅片）的选择性蚀刻以形成具有原始结构形状的空隙。 该空隙然后用作模具。 可流动介电材料填充空隙以形成与原始结构/模具相同的形状。 然后发生后处理（例如，氧化堆积和退火）以使空隙中的电介质硬化。 所得到的产品是模制的电介质纳米结构，其具有与原始结构相同的形状，但由不同的材料（例如电介质代替硅）构成。 本文描述了其它实施例。

公开(公告)号：US20140173716A1

公开(公告)日：2014-06-19

申请号：US13717433

申请日：2012-12-17

申请人： Sasikanth Manipatruni ,  Kelin J. Kuhn ,  Debendra Mallik ,  John C. Johnson

发明人： Sasikanth Manipatruni ,  Kelin J. Kuhn ,  Debendra Mallik ,  John C. Johnson

IPC分类号： G06F21/44

CPC分类号： G06F21/44 ,  G06F21/10 ,  G06F21/35

摘要： Managing and accessing personal data is described. In one example, an apparatus has an application processor, a memory to store data, a receive and a transmit array coupled to the application processor to receive data to store in the memory and to transmit data stored in the memory through a wireless interface, and an inertial sensor to receive user commands to authorize the processor to receive and transmit data through the receive and transmit array.

摘要翻译： 描述管理和访问个人数据。 在一个示例中，设备具有应用处理器，用于存储数据的存储器，耦合到应用处理器的接收和发送阵列，以接收存储在存储器中的数据并通过无线接口传输存储在存储器中的数据，以及 惯性传感器，用于接收用户命令，以授权处理器通过接收和发送阵列接收和发送数据。

公开(公告)号：US20140001441A1

公开(公告)日：2014-01-02

申请号：US13539195

申请日：2012-06-29

申请人： Seiyon Kim ,  Kelin J. Kuhn ,  Tahir Ghani ,  Anand S. Murthy ,  Mark Armstrong ,  Rafael Rios ,  Abhijit Jayant Pethe ,  Willy Rachmady

发明人： Seiyon Kim ,  Kelin J. Kuhn ,  Tahir Ghani ,  Anand S. Murthy ,  Mark Armstrong ,  Rafael Rios ,  Abhijit Jayant Pethe ,  Willy Rachmady

IPC分类号： H01L29/78 ,  H01L21/336 ,  B82Y40/00 ,  B82Y99/00

CPC分类号： H01L29/0673 ,  B82Y40/00 ,  H01L21/30604 ,  H01L21/3105 ,  H01L21/31155 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78 ,  H01L29/78696

摘要： A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

摘要翻译： 公开了一种具有多个内部间隔物的纳米线器件和用于形成所述内部间隔物的方法。 在一个实施例中，半导体器件包括设置在衬底上方的纳米线堆叠，纳米线堆叠具有多个垂直堆叠的纳米线，围绕多个纳米线中的每一个缠绕的栅极结构，限定器件的沟道区，栅极 结构，其具有栅极侧壁，在沟道区域的相对侧上的一对源极/漏极区域; 以及位于纳米线堆叠内部的两个相邻纳米线之间的栅极侧壁的一部分上的内部间隔物。 在一个实施例中，内部间隔物通过在与沟道区相邻蚀刻的凹坑中沉积间隔物形成。 在一个实施例中，通过沟道区蚀刻凹坑。 在另一个实施例中，通过源/漏区蚀刻凹坑。

公开(公告)号：US07999607B2

公开(公告)日：2011-08-16

申请号：US12775209

申请日：2010-05-06

申请人： Kelin J. Kuhn ,  Richard K. Hose, Jr. ,  Edward Burton ,  Rajesh Kumar

发明人： Kelin J. Kuhn ,  Richard K. Hose, Jr. ,  Edward Burton ,  Rajesh Kumar

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： H01L27/088

摘要： Power switch units for microelectronic devices are disclosed. In one aspect, a microelectronic device may include a functional circuit, and a power switch unit to switch power to the functional circuit on and off. The power switch unit may include a large number of transistors coupled together. The transistors may include predominantly positive-channel, insulated gate field effect transistors, which have a gate dielectric that includes a high dielectric constant material. Power switch units having such transistors may tend to have low power consumption. In an aspect, an overdrive voltage may be applied to the gates of such transistors to further reduce power consumption. Methods of overdriving such transistors and systems including such power switch units are also disclosed.

摘要翻译： 公开了用于微电子器件的功率开关单元。 一方面，微电子器件可以包括功能电路，以及电源开关单元，用于将功率电路接通和断开。 电源开关单元可以包括耦合在一起的大量晶体管。 晶体管可以包括主要为正沟道绝缘栅场效应晶体管，其具有包括高介电常数材料的栅极电介质。 具有这种晶体管的功率开关单元倾向于具有低功耗。 在一方面，可以将过驱动电压施加到这种晶体管的栅极，以进一步降低功耗。 还公开了过载驱动这种晶体管和包括这种功率开关单元的系统的方法。

公开(公告)号：US20100214005A1

公开(公告)日：2010-08-26

申请号：US12775209

申请日：2010-05-06

申请人： Kelin J. Kuhn ,  Richard K. Hose, JR. ,  Edward Burton ,  Rajesh Kumar

发明人： Kelin J. Kuhn ,  Richard K. Hose, JR. ,  Edward Burton ,  Rajesh Kumar

IPC分类号： H03K17/687

CPC分类号： H01L27/088

摘要： Power switch units for microelectronic devices are disclosed. In one aspect, a microelectronic device may include a functional circuit, and a power switch unit to switch power to the functional circuit on and off. The power switch unit may include a large number of transistors coupled together. The transistors may include predominantly positive-channel, insulated gate field effect transistors, which have a gate dielectric that includes a high dielectric constant material. Power switch units having such transistors may tend to have low power consumption. In an aspect, an overdrive voltage may be applied to the gates of such transistors to further reduce power consumption. Methods of overdriving such transistors and systems including such power switch units are also disclosed.

摘要翻译： 公开了用于微电子器件的功率开关单元。 一方面，微电子器件可以包括功能电路，以及电源开关单元，用于将功率电路接通和断开。 电源开关单元可以包括耦合在一起的大量晶体管。 晶体管可以包括主要为正沟道绝缘栅场效应晶体管，其具有包括高介电常数材料的栅极电介质。 具有这种晶体管的功率开关单元倾向于具有低功耗。 在一方面，可以将过驱动电压施加到这种晶体管的栅极，以进一步降低功耗。 还公开了过载驱动这种晶体管和包括这种功率开关单元的系统的方法。

公开(公告)号：US07737770B2

公开(公告)日：2010-06-15

申请号：US11394810

申请日：2006-03-31

申请人： Kelin J. Kuhn ,  Richard K. Hose, Jr. ,  Edward Burton ,  Rajesh Kumar

发明人： Kelin J. Kuhn ,  Richard K. Hose, Jr. ,  Edward Burton ,  Rajesh Kumar

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： H01L27/088

摘要： Power switch units for microelectronic devices are disclosed. In one aspect, a microelectronic device may include a functional circuit, and a power switch unit to switch power to the functional circuit on and off. The power switch unit may include a large number of transistors coupled together. The transistors may include predominantly positive-channel, insulated gate field effect transistors, which have a gate dielectric that includes a high dielectric constant material. Power switch units having such transistors may tend to have low power consumption. In an aspect, an overdrive voltage may be applied to the gates of such transistors to further reduce power consumption. Methods of overdriving such transistors and systems including such power switch units are also disclosed.

摘要翻译： 公开了用于微电子器件的功率开关单元。 一方面，微电子器件可以包括功能电路，以及电源开关单元，用于将功率电路接通和断开。 电源开关单元可以包括耦合在一起的大量晶体管。 晶体管可以包括主要为正沟道绝缘栅场效应晶体管，其具有包括高介电常数材料的栅极电介质。 具有这种晶体管的功率开关单元倾向于具有低功耗。 在一方面，可以将过驱动电压施加到这种晶体管的栅极，以进一步降低功耗。 还公开了过载驱动这种晶体管和包括这种功率开关单元的系统的方法。