Synthesis of N-[1-(chloromethyl)propyl]acetamide
    51.
    发明授权
    Synthesis of N-[1-(chloromethyl)propyl]acetamide 失效
    合成N- {8 1-(氯甲基)丙基{9乙酰胺

    公开(公告)号:US3944608A

    公开(公告)日:1976-03-16

    申请号:US493800

    申请日:1974-08-01

    申请人: Balwant Singh

    发明人: Balwant Singh

    IPC分类号: C07C103/34

    摘要: N-[1-(Chloromethyl)propyl]acetamide, for the synthesis of ethambutol hydrochloride, d,d'-2,2'-(ethylenediimino)-di-1-butanol dihydrochloride, is produced in high purity and good yields by the reaction of butene-1, a nitrile, preferably an excess of acetonitrile, and chlorine to form N-[1-(chloromethyl)propyl]acetimidoyl chloride which is hydrolyzed to N-[1-(chloromethyl)propyl]acetamide. This may be hydrolyzed further to dl-2-amino-1-butanol, which can be isolated as the hydrochloride, or free base, or a mixture, resolved with L(+)-tartaric acid and the d-2-amino-1-butanol reacted with ethylene dichloride and then hydrochloric acid to form ethambutol hydrochloride.

    摘要翻译: N- [1-(氯甲基)丙基]乙酰胺,用于合成乙胺丁醇盐酸盐,d,d'-2,2' - (乙二胺基) - 二-1-丁醇二盐酸盐,以高纯度和良好的产率由 丁烯-1,腈,优选过量的乙腈和氯反应形成N- [1-(氯甲基)丙基]亚氨代乙酰氯,将其水解成N- [1-(氯甲基)丙基]乙酰胺。 这可以进一步水解成dl-2-氨基-1-丁醇,其可以以盐酸盐或游离碱或混合物的形式分离,用L(+) - 酒石酸和d-2-氨基-1 - 丁醇与二氯乙烷反应,然后与盐酸反应生成盐酸乙胺丁醇。

    Photosensitive azido processes
    52.
    发明授权
    Photosensitive azido processes 失效
    光敏叠氮过程

    公开(公告)号:US3933497A

    公开(公告)日:1976-01-20

    申请号:US483483

    申请日:1974-06-27

    申请人: Balwant Singh

    发明人: Balwant Singh

    CPC分类号: G03C1/695

    摘要: Dry photoimaging processes and compositions employing photosensitive coatings of volatile peri-substituted aromatic azido compounds in a permeable film-forming plastic are disclosed.

    摘要翻译: 公开了在渗透性成膜塑料中使用挥发性邻位取代的芳族叠氮化合物的光敏涂层的干光学成像方法和组合物。

    Method and system for measuring maximum operating frequency and corresponding duty cycle for an I/O cell
    53.
    发明授权
    Method and system for measuring maximum operating frequency and corresponding duty cycle for an I/O cell 有权
    用于测量I / O单元的最大工作频率和相应占空比的方法和系统

    公开(公告)号:US07710101B2

    公开(公告)日:2010-05-04

    申请号:US11833779

    申请日:2007-08-03

    IPC分类号: G06F1/12 G06F1/04

    摘要: A circuit for measuring maximum operating frequency and its corresponding duty cycle for an input I/O cell implementation under test (IUT) includes a condition checking module, a central control module and a duty cycle measurement module. The condition checking module checks an upper threshold voltage and a lower threshold voltage. The central control module controls a plurality of operations for measuring the frequency. The duty cycle measurement module measures the duty cycle and finally all these modules together and calculates maximum operating frequency of the IUT.

    摘要翻译: 用于测量最大工作频率的电路及其相应的占空比(IUT)的输入I / O单元实现包括状态检查模块,中央控制模块和占空比测量模块。 条件检查模块检查上阈值电压和较低阈值电压。 中央控制模块控制用于测量频率的多个操作。 占空比测量模块测量占空比,最后测量所有这些模块,并计算IUT的最大工作频率。

    FLEXIBLE ON CHIP TESTING CIRCUIT FOR I/O'S CHARACTERIZATION
    54.
    发明申请
    FLEXIBLE ON CHIP TESTING CIRCUIT FOR I/O'S CHARACTERIZATION 有权
    芯片测试电路灵活的I / O特性

    公开(公告)号:US20090076753A1

    公开(公告)日:2009-03-19

    申请号:US12135418

    申请日:2008-06-09

    IPC分类号: G01R31/317

    CPC分类号: G01R31/31715

    摘要: The present invention provides a flexible on-chip testing circuit and methodology for measuring I/O characterization of multiple I/O structures. The testing circuit includes a register bank, a central processing controller (CPC), a character slew module, a delay characterization module, and a character frequency module. The register bank stores multiple instructions, and measurement results. The CPC fetches the instructions from the register bank. The CPC includes various primary and secondary state machines for interpreting the fetched instructions for execution. Depending on the input instruction the CPC applies stimulus to the IUT and the output of the IUT is used by the Local characterization modules (CHARMODULE) to extract the desired characterization parameters such as the character slew module which measures a voltage rise/fall time either for a single voltage IUT or a multi-voltage IUT. The Test Methodology for STIOBISC consists of an automated ATE pattern generation from verification test benches and automated result processing by converting the ATE data logs into the final readable format, thereby considerably reducing the test setup and output processing time. The testing circuit can operate in multiple modes for selecting one of these modules.

    摘要翻译: 本发明提供了用于测量多个I / O结构的I / O表征的灵活的片上测试电路和方法。 测试电路包括寄存器组,中央处理控制器(CPC),字符转换模块,延迟表征模块和字符频率模块。 注册银行存储多个指令和测量结果。 CPC从注册银行取得指示。 CPC包括用于解释获取的指令执行的各种主要和次要状态机。 根据输入指令,CPC对IUT应用激励,IUT的输出由本地表征模块(CHARMODULE)用于提取所需的特性参数,例如测量电压上升/下降时间的字符转换模块, 单电压IUT或多电压IUT。 STIOBISC的测试方法包括通过将ATE数据日志转换为最终可读格式的验证测试台和自动化结果处理的自动ATE模式生成,从而大大降低了测试设置和输出处理时间。 测试电路可以在多种模式下工作,以选择这些模块之一。

    On-chip storage memory for storing variable data bits
    55.
    发明授权
    On-chip storage memory for storing variable data bits 有权
    用于存储可变数据位的片上存储器

    公开(公告)号:US07372755B2

    公开(公告)日:2008-05-13

    申请号:US11102463

    申请日:2005-04-08

    IPC分类号: G11C7/00

    CPC分类号: G06F5/10 G11C7/1006

    摘要: An improved on-chip storage memory and method for storing variable data bits, the memory including an on-chip storage memory system for storing variable data bits that has a memory for storing data bits, a wrapper for converting the memory into a first-in first-out (FIFO) memory, and a controller for performing operations on the memory. In operation, the memory is converted into a FIFO memory after storing data, and output logic selects data to be output in a serial manner.

    摘要翻译: 一种用于存储可变数据位的改进的片上存储器和方法,所述存储器包括用于存储具有用于存储数据位的存储器的可变数据位的片上存储存储器系统,用于将存储器转换为先进先出 先进先出(FIFO)存储器和用于对存储器执行操作的控制器。 在操作中,存储器在存储数据之后被转换为FIFO存储器,并且输出逻辑选择要以串行方式输出的数据。

    On-chip and at-speed tester for testing and characterization of different types of memories
    56.
    发明授权
    On-chip and at-speed tester for testing and characterization of different types of memories 有权
    用于测试和表征不同类型存储器的片上和高速测试仪

    公开(公告)号:US07353442B2

    公开(公告)日:2008-04-01

    申请号:US11102556

    申请日:2005-04-08

    IPC分类号: G01R31/28

    摘要: An on-chip and at-speed tester for testing and characterization of different types of memories in an integrated circuit device, comprising a Centralized Flow Controller for automatically controlling the test operations for selected test programs, and Localized Signal Generators located inside each memory block and controlled by said Centralized Flow Controller for applying specified test patterns on the associated memory array.

    摘要翻译: 一种用于在集成电路设备中测试和表征不同类型的存储器的片上和速度测试器,包括用于自动控制所选测试程序的测试操作的集中流量控制器和位于每个存储块内的定位信号发生器,以及 由所述集中流量控制器控制,用于在相关联的存储器阵列上应用指定的测试图案。

    Measurement of timing skew between two digital signals

    公开(公告)号:US07058911B2

    公开(公告)日:2006-06-06

    申请号:US10321297

    申请日:2002-12-17

    申请人: Balwant Singh

    发明人: Balwant Singh

    IPC分类号: G06F17/50

    CPC分类号: G11C29/50012 G11C29/50

    摘要: A system for measuring a timing skew between two digital signals may include a clock generator for generating a time measurement clock, and a pulse-to-digital converter for converting the timing skew into an equivalent digital coded value after correcting for internal logic delays. The system may further include a register bank for storing the digital coded values, and a controller for generating control signals and sequences for controlling the operation of the pulse-to-digital converter and the register bank.

    On-chip analysis & computation of transition behaviour of embedded nets in integrated circuits
    58.
    发明申请
    On-chip analysis & computation of transition behaviour of embedded nets in integrated circuits 有权
    集成电路中嵌入式网络的过渡行为的片上分析与计算

    公开(公告)号:US20050174102A1

    公开(公告)日:2005-08-11

    申请号:US11025854

    申请日:2004-12-29

    IPC分类号: G01R19/00 G01R31/28 G01R31/30

    CPC分类号: G01R31/2884 G01R31/3004

    摘要: An apparatus for enabling the on-chip analysis of the voltage and/or current transition behaviour of one or more embedded nets of an integrated circuit independently of the fabrication process. The said apparatus comprises a Reference Step Generator (RSG) for providing programmable reference voltages or currents, a Step Delay Generator (SDG) for providing programmable delays, a Comparator (C) that receives the output of the reference step generator on one input, the output from the node under test at the second input, and a latch enable signal from the step delay generator, and provides a latched digital output in response to the comparison, and a controller that co-ordinates the operation of the reference step generator, Step Delay Generator and Latching Comparator to provide a transient response measurement.

    摘要翻译: 一种用于独立于制造过程实现片上分析集成电路的一个或多个嵌入网络的电压和/或电流转换特性的装置。 所述装置包括用于提供可编程参考电压或电流的参考步长发生器(RSG),用于提供可编程延迟的步进延迟发生器(SDG);在一个输入端接收参考步进发生器的输出的比较器(C) 在来自第二输入的被测节点的输出以及来自阶梯延迟发生器的锁存使能信号,并且响应于该比较而提供锁存的数字输出;以及控制器,其对参考步长发生器的操作进行调节,步骤 延迟发生器和锁存比较器提供瞬态响应测量。

    N-(substituted) maleimides and compositions incorporating the same
    60.
    发明授权
    N-(substituted) maleimides and compositions incorporating the same 失效
    N-(取代)马来酰亚胺及其组合物

    公开(公告)号:US5602205A

    公开(公告)日:1997-02-11

    申请号:US430051

    申请日:1995-04-27

    摘要: Novel polyfunctional maleimides as well as novel compositions based on mono- and polyfunctional maleimides are provided. Also provided are heat resistance resin compositions and curable compositions incorporating the same. The monofunctional maleimide is N-(2,3-dimethylphenyl)maleimide, and the polyfunctional maleimides are bis- and higher functional variations thereof.

    摘要翻译: 提供了新的多官能马来酰亚胺以及基于单官能和多官能马来酰亚胺的新型组合物。 还提供了耐热树脂组合物和包含其的可固化组合物。 单官能马来酰亚胺是N-(2,3-二甲基苯基)马来酰亚胺,多官能马来酰亚胺是其双功能和更高的功能变化。