公开(公告)号：US06127898A

公开(公告)日：2000-10-03

申请号：US5722

申请日：1998-01-12

申请人： David Naura

发明人： David Naura

IPC分类号： H03K3/0231 ,  H03K3/354 ,  H03K3/3565 ,  H03K19/094 ,  H03K3/356

CPC分类号： H03K3/354 ,  H03K3/0231 ,  H03K3/3565

摘要： A ring oscillator using CMOS technology having three logic gates, including a threshold amplifier, where the transistors that set the voltage rise threshold and the voltage drop threshold in the amplifier are controlled by a bias control circuit so that the ratio of voltage rise threshold to the voltage supply diminishes and the ratio of the voltage drop threshold to the voltage supply increases, when the supply voltage falls.

摘要翻译： 使用具有三个逻辑门的CMOS技术的环形振荡器，包括阈值放大器，其中设置放大器中的电压上升阈值和电压降阈值的晶体管由偏置控制电路控制，使得电压上升阈值与 当电源电压下降时，电压降低，电压降阈值与电源的比例增加。

公开(公告)号：US6125022A

公开(公告)日：2000-09-26

申请号：US193735

申请日：1998-11-17

申请人： David Naura

发明人： David Naura

IPC分类号： H03K17/22 ,  H02H3/00

CPC分类号： H03K17/223 ,  H03K17/22

摘要： The invention relates to a device to neutralize an electronic circuit when it is being powered or disconnected. It can be applied more particularly to electronic circuits powered by low voltages on the order of 1.8 volts. The device of the invention is not significantly affected by variations, due to manufacturing conditions, in the values of its components. The invention may be applied to the field of programmable electrical memories.

摘要翻译： 本发明涉及当电子电路被供电或断开时中和电路的装置。 它可以更具体地应用于由1.8伏数量级的低电压供电的电子电路。 本发明的装置不受制造条件在其组件的值中的变化的显着影响。 本发明可以应用于可编程电存储器领域。

公开(公告)号：US06034895A

公开(公告)日：2000-03-07

申请号：US198431

申请日：1998-11-24

申请人： David Naura ,  Jean Devin

发明人： David Naura ,  Jean Devin

IPC分类号： G11C16/12 ,  G11C16/14 ,  G11C16/04

CPC分类号： G11C16/14 ,  G11C16/12

摘要： A method and apparatus for the programming and erasure of a memory cell made out of floating-gate transistors and to the circuit pertaining thereto is described. It can be applied especially to non-volatile electrically erasable and programmable memories, for example EEPROMs and flash EPROMs. A programming voltage or erasure voltage comprising a voltage shift equal in value to a reference voltage is produced, followed by a voltage ramp comprising a rising phase followed possibly by voltage plateau, this voltage ramp being shifted in voltage by the value of the reference voltage and being followed, in turn, by a voltage drop. The value of the voltage shift is fixed at an intermediate value that is lower than the value of a so-called tunnel voltage of the memory cell but greater than the supply voltage.

摘要翻译： 描述了由浮栅晶体管制成的存储单元的编程和擦除以及与其有关的电路的方法和装置。 它可以特别适用于非易失性电可擦除和可编程存储器，例如EEPROM和闪存EPROM。 产生包括与参考电压值相等的电压偏移的编程电压或擦除电压，随后是包括可能伴随电压平台的上升相的电压斜坡，该电压斜坡在电压上移动参考电压的值， 随之而来的是电压降。 电压偏移的值固定在比存储单元的所谓的隧道电压的值低的值的中间值，但大于电源电压。

公开(公告)号：US5995416A

公开(公告)日：1999-11-30

申请号：US156945

申请日：1998-09-18

申请人： David Naura ,  Sebastien Zink

发明人： David Naura ,  Sebastien Zink

IPC分类号： G11C16/12 ,  H03K4/94 ,  G11C16/04

CPC分类号： G11C16/12 ,  H03K4/94

摘要： A method for the generation of voltage for the programming or erasure of a non-volatile memory cell is disclosed. Also disclosed is a circuit and a computer readable medium which implement the method. During an operation of programming or erasure in the memory, the slope P of the write voltage ramp is adapted to the number of memory cells to be programmed or erased simultaneously during this operation. This method is particularly useful in the field of non-volatile, electrically erasable and programmable memories.

摘要翻译： 公开了一种用于产生用于非易失性存储单元的编程或擦除的电压的方法。 还公开了实现该方法的电路和计算机可读介质。 在存储器中的编程或擦除操作期间，写入电压斜坡的斜率P适于在该操作期间同时编程或擦除的存储器单元的数量。 该方法在非易失性，电可擦除和可编程存储器领域特别有用。

公开(公告)号：US5946241A

公开(公告)日：1999-08-31

申请号：US908322

申请日：1997-08-07

申请人： Sebastien Zink ,  David Naura

发明人： Sebastien Zink ,  David Naura

IPC分类号： G11C7/06 ,  G11C16/28 ,  G11C7/00

CPC分类号： G11C7/065 ,  G11C16/28 ,  G11C7/062

摘要： The disclosure relates to the field of memories in integrated circuit form. It can be applied more particularly to the field of EPROM or EEPROM type electrically programmable non-volatile memories. A memory array and read circuits are proposed in order to improve the time taken to read a data element. During a reading operation a read circuit is connected firstly to an erased cell and secondly to a programmed cell. The memory outputs a 1 for a read operation that access a first memory cell having an erased state and a second memory cell having a programmed cell, and further, the memory outputs a 0 for a read operation that access a first memory cell having a programmed state and a second memory cell having an erased state.

摘要翻译： 本公开涉及集成电路形式的存储器领域。 它可以更具体地应用于EPROM或EEPROM型电可编程非易失性存储器的领域。 提出了存储器阵列和读取电路，以便改善读取数据元素所需的时间。 在读取操作期间，读取电路首先连接到已擦除的单元，其次连接到编程单元。 存储器输出1用于访问具有擦除状态的第一存储器单元的读取操作和具有编程单元的第二存储器单元，此外，存储器输出0用于访问具有编程单元的第一存储器单元的读取操作 状态和具有擦除状态的第二存储单元。