公开(公告)号：US6008516A

公开(公告)日：1999-12-28

申请号：US120837

申请日：1998-07-22

申请人： Friedoon Mehrad ,  Cetin Kaya

发明人： Friedoon Mehrad ,  Cetin Kaya

IPC分类号： H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11519 ,  H01L27/115

摘要： A FLASH EPROM layout with straight gate and isolation structures to improve scalability and eliminate the need for self-aligned source process.

摘要翻译： 具有直门和隔离结构的FLASH EPROM布局，以提高可扩展性，并消除对自对准源工艺的需要。

公开(公告)号：US5858839A

公开(公告)日：1999-01-12

申请号：US752092

申请日：1996-11-20

申请人： Cetin Kaya ,  Kemal Tamer San

发明人： Cetin Kaya ,  Kemal Tamer San

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： This invention provides a cost-effective, easy-to-integrate Flash EPROM cell array. Starting with a substrate (31) of first conductivity-type, a first diffusion (30) of second conductivity-type forms the sources (11), and the connections between sources, of all of the memory cells (10) of the array. A second diffusion (32) of first conductivity-type forms the channel of at least one memory cell (10) in the array. A floating gate (13) and a control gate (14) of that memory cell (10) are located over, and insulated from, a junction of the first diffusion and the second diffusion. A third diffusion (33) of second conductivity-type is isolated in the second diffusion (32) to form the drain (12) of the memory cell (10). During operation, only positive voltages may be used for programming and erasing of the cells (10), thus eliminating the need for negative voltages and for triple-well diffusions. The cell array of this invention requires little or no current for Fowler-Nordheim erase operation. Therefore, there is no need for wordline (15) decoding of large arrays. In addition to the above features, use of the cell array of this invention saves space by eliminating, in certain types of prior-art arrays, the need for space-consuming columnar metal source lines. In that same type of array, a self-aligned-source etch step and a self-aligned-source implant step are eliminated.

摘要翻译： 本发明提供了一种成本有效的易于集成的闪存EPROM单元阵列。 从第一导电类型的衬底（31）开始，第二导电类型的第一扩散（30）形成源极（11）以及阵列的所有存储器单元（10）的源极之间的连接。 第一导电型的第二扩散（32）形成阵列中的至少一个存储单元（10）的沟道。 该存储单元（10）的浮动栅极（13）和控制栅极（14）位于第一扩散部分和第二扩散部分之间并与其绝缘。 在第二扩散（32）中隔离第二导电类型的第三扩散（33）以形成存储单元（10）的漏极（12）。 在操作期间，只有正电压可用于对电池（10）进行编程和擦除，从而消除对负电压和三阱扩散的需要。 本发明的电池阵列对于Fowler-Nordheim擦除操作需要很少的或没有电流。 因此，不需要对大阵列进行字线（15）解码。 除了上述特征之外，本发明的电池阵列的使用通过在某些类型的现有技术的阵列中消除对空间消耗的柱状金属源极线的需求来节省空间。 在相同类型的阵列中，消除了自对准源蚀刻步骤和自对准源注入步骤。

公开(公告)号：US5821581A

公开(公告)日：1998-10-13

申请号：US93517

申请日：1993-07-19

申请人： Cetin Kaya ,  Howard Tigelaar

发明人： Cetin Kaya ,  Howard Tigelaar

IPC分类号： G11C11/412 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L29/780

CPC分类号： G11C16/0425 ,  H01L29/42324 ,  H01L29/7885 ,  Y10S438/981

摘要： A non-volatile split-gate memory cell 8 which can be programmed with only a five volt power supply and is fabricated using standard transistor processing methods, comprises a semiconductor substrate 10 with a source 12 and a drain 14 region separated by a channel region 16. A conductive floating gate 18 is formed over a portion 16a of the channel region 16 and separated by a FAMOS oxide 20. A conductive control gate 22 is formed over but electrically insulated from the floating gate 18 and over a second portion 16b of the channel region 16. The control gate 22 is separated from the second portion of the channel 16b by a pass oxide 26 which is thicker than the FAMOS oxide 20. Other embodiments and processes are also disclosed.

公开(公告)号：US5646430A

公开(公告)日：1997-07-08

申请号：US520350

申请日：1995-08-28

申请人： Cetin Kaya ,  David Liu

发明人： Cetin Kaya ,  David Liu

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11517 ,  H01L27/115 ,  H01L29/7886

摘要： In one embodiment, a non-volatile memory structure 10 comprises heavily doped source 11 and drain 12 regions formed in the surface of a semiconductor substrate 8 and separated by a channel region. 21. A floating gate 13 is formed over and insulated from the channel region 21 and a control gate 14 is formed over and insulated from the floating gate 13. A lightly doped region 20 is formed in the channel 21 beneath the floating gate 13 and adjoining the source region 11. The lightly doped region 20 is spaced from the surface of said substrate 8. Other embodiments and processes are also disclosed.

摘要翻译： 在一个实施例中，非易失性存储器结构10包括形成在半导体衬底8的表面中并被沟道区分隔开的重掺杂源极11和漏极12区域。 浮动栅极13形成在沟道区域21的上方并与沟道区域21绝缘，并且控制栅极14形成在浮置栅极13之上并与浮动栅极13绝缘。轻掺杂区域20形成在浮动栅极13下方的沟道21中并且邻接 源区域11.轻掺杂区域20与所述衬底8的表面间隔开。还公开了其它实施例和工艺。

公开(公告)号：US5412603A

公开(公告)日：1995-05-02

申请号：US239008

申请日：1994-05-06

申请人： John F. Schreck ,  Cetin Kaya ,  David J. McElroy

发明人： John F. Schreck ,  Cetin Kaya ,  David J. McElroy

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C7/00

CPC分类号： G11C16/30 ,  G11C16/12 ,  G11C16/16

摘要： The drain-to-source voltage and current for programming a selected nonvolatile memory cell 10 are achieved efficiently by pumping the source 11 of a selected cell 11 to a voltage less than the voltage VSS at the reference-voltage terminal of the memory cell array while, at the same time, pumping the drain 12 of the selected cell 10 to a voltage greater than the voltage VCC, which may be 3 V, at the supply-voltage terminal of the memory cell array. The cell substrate W2 is pumped to a voltage close to the voltage of the source 11 and, optionally, below the voltage of the source 11. One or more simple charge-pump circuits convert the output of the voltage supply VCC to a source-drain voltage and current capable of programming the selected nonvolatile cell 10 by hot carrier injection.

摘要翻译： 通过将所选择的单元11的源极11泵送到小于存储单元阵列的参考电压端子处的电压VSS的电压来有效地实现用于对选定的非易失性存储单元10进行编程的漏极到源极电压和电流，同时 同时，在存储单元阵列的电源电压端将泵浦所选单元10的漏极12的电压大于可以为3V的电压VCC。 电池基板W2被泵浦到接近源极11的电压的电压，并且可选地低于源11的电压。一个或多个简单的电荷泵电路将电压源VCC的输出转换为源极 - 漏极 能够通过热载流子注入对所选择的非易失性电池10进行编程的电压和电流。