公开(公告)号：US20120011482A1

公开(公告)日：2012-01-12

申请号：US12832180

申请日：2010-07-08

申请人： Chuck ALPERT ,  Zhuo Li ,  Arjen Alexander Mets ,  Ying Zhou

发明人： Chuck ALPERT ,  Zhuo Li ,  Arjen Alexander Mets ,  Ying Zhou

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/08

摘要： A method, system, and computer usable program product for multiple threshold voltage cell families (mVt families) based integrated circuit design are provided in the illustrative embodiments. The integrated circuit includes cells, and a cell includes an electronic component. A design process is initialized by using cells from the mVt families in the design. The cells from the mVt families are included in iterative manipulation of the design. The cells from the mVt families are further included in violation cleanup and subsequent steps of the design process. A version of the design is produced that is usable to implement the circuit with the cells from the mVt families.

摘要翻译： 在说明性实施例中提供了用于多个阈值电压单元族（mVt系列）的集成电路设计的方法，系统和计算机可用程序产品。 集成电路包括单元，单元包括电子元件。 通过使用设计中的mVt系列的单元格初始化设计过程。 来自mVt系列的单元格被包含在设计的迭代操作中。 来自mVt系列的单元格进一步包含在违规清理和设计过程的后续步骤中。 产生了一种可用于使用来自mVt系列的单元实现电路的设计版本。

公开(公告)号：US07392493B2

公开(公告)日：2008-06-24

申请号：US10996292

申请日：2004-11-22

申请人： Charles Jay Alpert ,  Zhuo Li ,  Stephen Thomas Quay

发明人： Charles Jay Alpert ,  Zhuo Li ,  Stephen Thomas Quay

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5036

摘要： A method of determining buffer insertion locations in an integrated circuit design establishes candidate locations for inserting buffers into a net, and selects buffer insertion locations from among the candidates based on slew constraints. The selection of buffer insertion locations preferably optimizes slack and buffer cost while keeping slew from any buffered node to any sink less than a required slew rate. The slew analysis computes an output slew SL(v) of a given buffer b inserted at a node v as SL(v)=RS(b)·C(v)+KS(b), where C(v) is the downstream capacitance at v, RS(b) is the slew resistance of buffer b, and KS(b) is the intrinsic slew of buffer b. The delay through a given buffer may also be computed based on signal polarity. However, the invention still preferably uses worst-case slew resistance and intrinsic slew in considering the slew constraints. If the selection of the buffer insertion locations results in no locations being selected due to slew violations, the present invention may advantageously find a partial solution by relaxing the slew constraint.

摘要翻译： 在集成电路设计中确定缓冲器插入位置的方法建立了用于将缓冲器插入网络的候选位置，并且基于回转约束从候选中选择缓冲器插入位置。 缓冲器插入位置的选择优选地优化松弛和缓冲器成本，同时保持从任何缓冲节点转到任何小于所需转换速率的接收端。 滑动分析计算插入在节点v处的给定缓冲器b的输出滑动SL（v）为SL（v）= RS（b）.C（v）+ KS（b），其中C（v）是下游 电容在v，RS（b）是缓冲器b的耐压，KS（b）是缓冲器b的固有电压。 也可以基于信号极性来计算给定缓冲器的延迟。 然而，本发明在考虑压摆约束的情况下仍然优选地使用最坏情况的耐回转电阻和固有的电压。 如果缓冲器插入位置的选择导致没有被选择的位置，因为本发明可以通过放松压摆约束来有利地找到部分解决方案。

公开(公告)号：US20080072202A1

公开(公告)日：2008-03-20

申请号：US11947706

申请日：2007-11-29

申请人： Charles Alpert ,  Zhuo Li ,  Stephen Quay

发明人： Charles Alpert ,  Zhuo Li ,  Stephen Quay

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5036

摘要： A method of determining buffer insertion locations in an integrated circuit design establishes candidate locations for inserting buffers into a net, and selects buffer insertion locations from among the candidates based on slew constraints. The selection of buffer insertion locations preferably optimizes slack and buffer cost while keeping slew from any buffered node to any sink less than a required slew rate. The slew analysis computes an output slew SL(v) of a given buffer b inserted at a node v as SL(v)=RS(b)·C(v)+KS(b), where C(v) is the downstream capacitance at v, RS(b) is the slew resistance of buffer b, and KS(b) is the intrinsic slew of buffer b. The delay through a given buffer may also be computed based on signal polarity. However, the invention still preferably uses worst-case slew resistance and intrinsic slew in considering the slew constraints. If the selection of the buffer insertion locations results in no locations being selected due to slew violations, the present invention may advantageously find a partial solution by relaxing the slew constraint.

摘要翻译： 在集成电路设计中确定缓冲器插入位置的方法建立了用于将缓冲器插入网络的候选位置，并且基于回转约束从候选中选择缓冲器插入位置。 缓冲器插入位置的选择优选地优化松弛和缓冲器成本，同时保持从任何缓冲节点转到任何小于所需转换速率的接收端。 滑动分析计算插入在节点v处的给定缓冲器b的输出滑动SL（v）为SL（v）= RS（b）.C（v）+ KS（b），其中C（v）是下游 电容在v，RS（b）是缓冲器b的耐压，KS（b）是缓冲器b的固有电压。 也可以基于信号极性来计算给定缓冲器的延迟。 然而，本发明在考虑压摆约束的情况下仍然优选地使用最坏情况的耐回转电阻和固有的电压。 如果缓冲器插入位置的选择导致没有被选择的位置，因为本发明可以通过放松压摆约束来有利地找到部分解决方案。

公开(公告)号：US20060121895A1

公开(公告)日：2006-06-08

申请号：US11273886

申请日：2005-11-15

申请人： Fengshao Zou ,  Wenxian Li ,  Zhuo Li ,  Jianghai Gao ,  Shikui Guo

发明人： Fengshao Zou ,  Wenxian Li ,  Zhuo Li ,  Jianghai Gao ,  Shikui Guo

IPC分类号： H04Q7/20 ,  H04M3/16

CPC分类号： H04L63/0853 ,  H04L63/162 ,  H04W12/06

摘要： Disclosed is a method for implementing authentication of high rate packet data (HRPD) services, applicable to multi-mode networks including IS95/CDMA2000 1x and CDMA2000 HRPD networks. The method includes an Access Terminal (AT) using the user information in the User Identity Module (UIM) as the user identifier and starting an authentication in accordance with the Extended Authentication Protocol (EAP). A Mobile Switching Center (MSC)/Visiting Location Register (VLR) obtains a random number and a first authentication number based on the user identifier, and the AT calculates a second authentication number based on said random number. The MSC/VLR compares the first authentication number with the second authentication number to determine whether they are consistent. If consistent, the authentication is successful. Otherwise, the authentication is aborted. With the disclosed method, authentication can be made by using the original MSC and HLR/AC in the CDMA IS95 or CDMA2000 1x network. The method allows low cost and easy operation for the user as well as convenient maintenance for the operator.

公开(公告)号：US08495548B2

公开(公告)日：2013-07-23

申请号：US13248711

申请日：2011-09-29

申请人： Kanak Behari Agarwal ,  Charles Jay Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  Natarajan Viswanathan

发明人： Kanak Behari Agarwal ,  Charles Jay Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F2217/12 ,  Y02P90/265

摘要： A method, system, and computer program product for multi-patterning lithography (MPL) aware cell placement in integrated circuit (IC) design are provided in the illustrative embodiments. A global phase of cell movement is performed. A local phase cell movement is performed, wherein the local phase includes moving a color instance of the cell from a plurality of color instances of the cell within a row of cell in the IC design, wherein the global phase and the local phase are each performed before a final placement is produced for the IC design.

摘要翻译： 在说明性实施例中提供了用于集成电路（IC）设计中的多图案化光刻（MPL）感知单元放置的方法，系统和计算机程序产品。 执行细胞运动的全局阶段。 执行局部相位单元移动，其中本地相位包括从IC设计中的单元行内的单元的多个颜色实例移动单元的颜色实例，其中，每个执行全局相位和局部相位 在为IC设计制作最终布局之前。

公开(公告)号：US20120284683A1

公开(公告)日：2012-11-08

申请号：US13102776

申请日：2011-05-06

申请人： Charles Jay Alpert ,  Zhuo Li ,  Stephen Thomas Quay ,  Ying Zhou

发明人： Charles Jay Alpert ,  Zhuo Li ,  Stephen Thomas Quay ,  Ying Zhou

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5077 ,  G06F2217/84

摘要： A method, system, and computer program product for timing driven routing in a design of an integrated circuit (IC) are provided in the illustrative embodiments. A router application executing in a data processing system performs a pre-global routing optimization of the design. A plurality of wirelength target constraints are set on a plurality of subsets of a set of nets in the design. Global routing is performed on the design. The design is adjusted using wires placed in the design during the global routing. A priority is assigned to each net in the set of nets. Detailed routing is performed on the design.

摘要翻译： 在说明性实施例中提供了用于在集成电路（IC）的设计中的定时驱动路由的方法，系统和计算机程序产品。 在数据处理系统中执行的路由器应用程序执行设计的全局前路由优化。 在设计中的一组网络的多个子集上设置多个线长目标约束。 在设计上执行全局路由。 在全局路由期间，使用设计中的电线来调整设计。 优先级分配给网络集合中的每个网络。 在设计上执行详细的路由。

公开(公告)号：US20100313070A1

公开(公告)日：2010-12-09

申请号：US12477361

申请日：2009-06-03

申请人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Zhuo Li ,  Sani R. Nassif

发明人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Zhuo Li ,  Sani R. Nassif

IPC分类号： G06F11/26

CPC分类号： G06F11/008

摘要： A failure probability for a system having multi-fail regions is computed by generating failure directions in a space whose dimensions are the system parameters under consideration. The failure directions are preferably uniform, forming radial slices. The failure directions may be weighted. The radial slices have fail boundaries defining fail regions comparable to broken shells. The distribution of the system parameters is integrated across the broken shell regions to derive a failure contribution for each failure direction. The failure probability is the sum of products of each failure contribution and its weight. Failure contributions are computed using equivalent expressions dependent on the number of dimensions, which can be used to build lookup tables for normalized fail boundary radii. The entire process can be iteratively repeated with successively increasing failure directions until the failure probability converges. The method is particularly useful in analyzing failure probability of electrical circuits such as memory cells.

摘要翻译： 通过在尺寸为所考虑的系统参数的空间中生成故障方向来计算具有多故障区域的系统的故障概率。 故障方向优选均匀，形成径向切片。 失败方向可能被加权。 径向切片的失效边界定义与断裂壳相当的失效区域。 系统参数的分布在破裂的外壳区域中集成，以导出每个故障方向的故障贡献。 故障概率是每个失效贡献的乘积和其重量之和。 使用等同表达式计算故障贡献，取决于维数，可用于构建归一化失效边界半径的查找表。 可以连续增加故障方向，迭代重复整个过程，直到故障概率收敛。 该方法在分析诸如存储器单元之类的电路的故障概率方面特别有用。

公开(公告)号：US07299442B2

公开(公告)日：2007-11-20

申请号：US11032878

申请日：2005-01-11

申请人： Charles Jay Alpert ,  Zhuo Li ,  Stephen Thomas Quay

发明人： Charles Jay Alpert ,  Zhuo Li ,  Stephen Thomas Quay

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A method of estimating routing congestion between pins in a net of an integrated circuit design, by establishing one or more potential routes between the pins which pass through buckets in the net, assigning a probabilistic usage to each bucket based on any partial blockage of the wiring tracks in each bucket, and computing routing congestion for each bucket using its probabilistic usage. When the net is a two-pin net that is a part of a larger multi-pin net, and a tree is constructed to bridge the two-pin net to another pin of the multi-pin net. The routing congestion for each bucket is computed as a ratio of the bucket usage to bucket capacity. For L-shaped routes (having at least one bend in a bucket), the probabilistic usage is proportional to a scale factor a which is a ratio of a minimum number of available wiring tracks for a given route to a sum of minimum numbers of available wiring tracks for all possible routes. For Z-shaped routes (having at least two bends in two respective buckets), the probabilistic usage is equal to a ratio of a minimum capacity of a given route to a sum of minimum capacities of all routes having an associated orientation with the given route. Assignment of the usage values may entail the creation of a temporary usage map of the net buckets with an initial value of zero usage in every temporary usage map bucket, thereafter storing usage values in corresponding buckets of the temporary usage map, and deriving a final usage map from the temporary usage map.

摘要翻译： 一种在集成电路设计的网络中估计引脚之间的路由拥塞的方法，通过在通过网络中的网段的引脚之间建立一个或多个潜在路由，基于线路的任何部分阻塞向每个分组分配概率使用 每个桶中的轨道，以及使用其概率使用来计算每个桶的路由拥塞。 当网是作为较大多针网的一部分的双引脚网络，并且构造一棵树将双引脚网络桥接到多引脚网的另一个引脚。 每个桶的路由拥塞被计算为桶使用量与桶容量的比率。 对于L形路径（在桶中至少有一个弯道），概率使用与比例因子a成比例，比例因子a是给定路线的可用线路的最小数量与可用的最小数量之和的比率 所有可能的路线的线路。 对于Z形路线（在两个相应的桶中具有至少两个弯曲），概率使用等于给定路由的最小容量与具有与给定路由相关联的定向的所有路由的最小容量之和的比率 。 使用值的分配可能需要在每个临时使用地图桶中创建具有零使用的初始值的网络桶的临时使用图，然后将使用值存储在临时使用映射的相应桶中，并且导出最终使用 从临时使用地图映射。

公开(公告)号：US20130096976A1

公开(公告)日：2013-04-18

申请号：US13275609

申请日：2011-10-18

申请人： Charles Jay Alpert ,  Peter Feldmann ,  Zhuo Li ,  Ying Liu ,  Sani Richard Nassif

发明人： Charles Jay Alpert ,  Peter Feldmann ,  Zhuo Li ,  Ying Liu ,  Sani Richard Nassif

IPC分类号： G06Q10/06

CPC分类号： G06Q10/06 ,  G06Q10/0631

摘要： A method, system, and computer program product for designing a cost-effective and reliable distribution network for a utility are provided in the illustrative embodiments. A graph connecting a set of consumers of the utility with a set of suppliers of the utility is reduced to form a plurality of clusters. A first network between a supplier and a subset of consumers in a first cluster in the plurality of clusters is improved, the improving adding a first connection in the first network to provide continuity of supply of the utility to the subset of consumers after a predetermined number of failures in the first network. A design is generated for a second network connecting the set of suppliers to the set of consumers, the second network including the first network after the improving, wherein the second network has a cost that is within a lower threshold and an upper threshold.

摘要翻译： 在说明性实施例中提供了用于设计用于公用事业的成本有效且可靠的分配网络的方法，系统和计算机程序产品。 将该实用程序的一组消费者与该公用事业的一组供应商连接的图被减少以形成多个集群。 提高了在多个群集中的第一群集中的供应商和消费者子集之间的第一网络，改进了在第一网络中添加第一连接以在预定数量之后提供对消费者子集的效用的连续性 的第一个网络中的故障。 生成用于将供应商集合连接到消费者集合的第二网络的设计，包括第一网络在内的第二网络在改进之后，其中第二网络具有低于阈值和较高阈值的成本。

公开(公告)号：US07676780B2

公开(公告)日：2010-03-09

申请号：US11947706

申请日：2007-11-29

申请人： Charles Jay Alpert ,  Zhuo Li ,  Stephen Thomas Quay

发明人： Charles Jay Alpert ,  Zhuo Li ,  Stephen Thomas Quay

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5036

摘要： A method of determining buffer insertion locations in an integrated circuit design establishes candidate locations for inserting buffers into a net, and selects buffer insertion locations from among the candidates based on slew constraints. The selection of buffer insertion locations preferably optimizes slack and buffer cost while keeping slew from any buffered node to any sink less than a required slew rate. The slew analysis computes an output slew SL(v) of a given buffer b inserted at a node v as SL(v)=RS(b)·C(v)+KS(b), where C(v) is the downstream capacitance at v, RS(b) is the slew resistance of buffer b, and KS(b) is the intrinsic slew of buffer b. The delay through a given buffer may also be computed based on signal polarity. However, the invention still preferably uses worst-case slew resistance and intrinsic slew in considering the slew constraints. If the selection of the buffer insertion locations results in no locations being selected due to slew violations, the present invention may advantageously find a partial solution by relaxing the slew constraint.

摘要翻译： 在集成电路设计中确定缓冲器插入位置的方法建立了用于将缓冲器插入网络的候选位置，并且基于回转约束从候选中选择缓冲器插入位置。 缓冲器插入位置的选择优选地优化松弛和缓冲器成本，同时保持从任何缓冲节点转到任何小于所需转换速率的接收端。 转换分析计算插入节点v的给定缓冲器b的输出转换SL（v）为SL（v）= RS（b）·C（v）+ KS（b），其中C（v）是下游 电容在v，RS（b）是缓冲器b的耐压，KS（b）是缓冲器b的固有电压。 也可以基于信号极性来计算给定缓冲器的延迟。 然而，本发明在考虑压摆约束的情况下仍然优选地使用最坏情况的耐回转电阻和固有的电压。 如果缓冲器插入位置的选择导致没有被选择的位置，因为本发明可以通过放松压摆约束来有利地找到部分解决方案。