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公开(公告)号：US20110272763A1
公开(公告)日：2011-11-10
申请号：US13144059
申请日：2009-12-17
申请人： Yuichiro Sasaki , Katsumi Okashita , Bunji Mizuno
发明人： Yuichiro Sasaki , Katsumi Okashita , Bunji Mizuno
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/66803 , H01L29/7854
摘要： Extension regions (17) are provided in side portions of a fin-shaped semiconductor region (13) formed on a substrate (11). A gate electrode (15) is formed to extend across the fin-shaped semiconductor region (13) and to be adjacent to the extension regions (17). A resistance region (37) having a resistivity higher than that of the extension regions (17) is formed in an upper portion of the fin-shaped semiconductor region (13) adjacent to the gate electrode (15).
摘要翻译： 延伸区域（17）设置在形成在基板（11）上的鳍状半导体区域（13）的侧部。 栅电极（15）形成为跨越鳍状半导体区域（13）延伸并且与延伸区域（17）相邻。 在与栅极（15）相邻的鳍状半导体区域（13）的上部形成电阻率高于延伸区域（17）的电阻区域（37）。
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公开(公告)号：US20110065266A1
公开(公告)日：2011-03-17
申请号：US12517477
申请日：2008-09-03
IPC分类号： H01L21/22
CPC分类号： H01L21/2236 , H01J37/32412 , H01L29/6659
摘要： A substrate is exposed to a plasma generated from a gas containing an impurity, thereby doping a surface portion of the substrate with the impurity and thus forming an impurity region. A predetermined plasma doping time is used, which is included within a time range over which a deposition rate on the substrate by the plasma is greater than 0 nm/min and less than or equal to 5 nm/min.
摘要翻译： 将衬底暴露于由含有杂质的气体产生的等离子体，从而用杂质掺杂衬底的表面部分，从而形成杂质区域。 使用预定的等离子体掺杂时间，其包括在等离子体在衬底上的沉积速率大于0nm / min且小于或等于5nm / min的时间范围内。
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公开(公告)号：US20100255615A1
公开(公告)日：2010-10-07
申请号：US12741132
申请日：2008-10-02
IPC分类号： H01L21/66 , H01L21/383 , H01L21/479
CPC分类号： H01L21/2236 , H01L29/66803 , H01L29/7854
摘要： A fin-shaped semiconductor region is formed on a substrate, and then the substrate is placed in a chamber. Then, an ignition gas is introduced into a chamber to thereby turn the ignition gas into a plasma, and then a process gas containing an impurity is introduced into the chamber to thereby turn the process gas into a plasma. Then, a bias voltage is applied to the substrate so as to dope the semiconductor region with the impurity after confirming attenuation of an amount of the ignition gas remaining in the chamber.
摘要翻译： 在基板上形成鳍状半导体区域，然后将基板放置在室内。 然后，将点火气体引入室中，从而将点火气体转化为等离子体，然后将含有杂质的工艺气体引入室中，从而将工艺气体转化为等离子体。 然后，在确认残留在室中的点火气体的量的衰减之后，将偏置电压施加到衬底，以便掺杂杂质。
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54.发明授权Method for producing a semiconductor device have fin-shaped semiconductor regions 有权制造半导体器件的方法具有鳍状半导体区域公开(公告)号：US08536000B2
公开(公告)日：2013-09-17
申请号：US13185221
申请日：2011-07-18
IPC分类号： H01L21/8238 , H01L21/8234 , H01L21/336
CPC分类号： H01L29/66803 , H01L29/66795 , H01L29/7854
摘要： First and second gate insulating films are formed so as to cover at least the upper corner of first and second fin-shaped semiconductor regions. The radius of curvature r1′ of the upper corner of the first fin-shaped semiconductor region located outside the first gate insulating film is greater than the radius of curvature r1 of the upper corner of the first fin-shaped semiconductor region located under the first gate insulating film and is less than or equal to 2×r1. The radius of curvature r2′ of the upper corner of the second fin-shaped semiconductor region located outside the second gate insulating film is greater than the radius of curvature r2 of the upper corner of the second fin-shaped semiconductor region located under the second gate insulating film and is less than or equal to 2×r2.
摘要翻译： 第一和第二栅极绝缘膜形成为至少覆盖第一和第二鳍状半导体区域的上角。 位于第一栅极绝缘膜外侧的第一鳍状半导体区域的上角的曲率半径r1'大于位于第一栅极下方的第一鳍状半导体区域的上角的曲率半径r1 绝缘膜，小于或等于2×r1。 位于第二栅极绝缘膜外侧的第二鳍状半导体区域的上角的曲率半径r2'大于位于第二栅极下方的第二鳍状半导体区域的上角的曲率半径r2 绝缘膜，小于或等于2×r2。
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公开(公告)号：US08258585B2
公开(公告)日：2012-09-04
申请号：US12676102
申请日：2009-04-30
IPC分类号： H01L27/088
CPC分类号： H01L29/785 , H01L29/66803
摘要： A semiconductor device includes: a fin-type semiconductor region (13) formed on a substrate (11); a gate insulating film (14) formed so as to cover an upper surface and both side surfaces of a predetermined portion of the fin-type semiconductor region (13); a gate electrode (15) formed on the gate insulating film (14); and an impurity region (17) formed on both sides of the gate electrode (15) in the fin-type semiconductor region (13). An impurity blocking portion (15a) for blocking the introduction of impurities is provided adjacent both sides of the gate electrode (15) over an upper surface of the fin-type semiconductor region (13).
摘要翻译： 半导体器件包括：形成在衬底（11）上的鳍状半导体区域（13）; 形成为覆盖所述鳍状半导体区域（13）的预定部分的上表面和两个侧面的栅极绝缘膜（14）; 形成在栅极绝缘膜（14）上的栅电极（15）; 以及形成在鳍式半导体区域（13）中的栅电极（15）的两侧的杂质区域（17）。 在鳍型半导体区域（13）的上表面上，在栅电极（15）的两侧附近设置用于阻止引入杂质的杂质阻挡部（15a）。
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公开(公告)号：US08124507B2
公开(公告)日：2012-02-28
申请号：US12937169
申请日：2010-03-04
申请人： Yuichiro Sasaki , Katsumi Okashita , Bunji Mizuno
发明人： Yuichiro Sasaki , Katsumi Okashita , Bunji Mizuno
IPC分类号： H01L29/78 , H01L21/223
CPC分类号： H01L29/785 , H01L29/66795
摘要： A fin-type semiconductor region (103) is formed on a substrate (101), and then a resist pattern (105) is formed on the substrate (101). An impurity is implanted into the fin-type semiconductor region (103) by a plasma doping process using the resist pattern (105) as a mask, and then at least a side of the fin-type semiconductor region (103) is covered with a protective film (107). Thereafter, the resist pattern (105) is removed by cleaning using a chemical solution, and then the impurity implanted into the fin-type semiconductor region (103) is activated by heat treatment.
摘要翻译： 在基板（101）上形成翅片型半导体区域（103），然后在基板（101）上形成抗蚀图案（105）。 通过使用抗蚀剂图案（105）作为掩模的等离子体掺杂工艺将杂质注入到鳍式半导体区域（103）中，然后用鳍状半导体区域（103）的至少一侧覆盖 保护膜（107）。 此后，通过使用化学溶液的清洗除去抗蚀剂图案（105），然后通过热处理激活注入到鳍式半导体区域（103）中的杂质。
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公开(公告)号：US20110147813A1
公开(公告)日：2011-06-23
申请号：US12944224
申请日：2010-11-11
申请人： Yuichiro Sasaki , Katsumi Okashita , Bunji Mizuno
发明人： Yuichiro Sasaki , Katsumi Okashita , Bunji Mizuno
IPC分类号： H01L29/772 , H01L21/22
CPC分类号： H01L29/785 , H01L21/2236 , H01L29/66795
摘要： A method for fabricating a semiconductor device includes: forming a fin-type semiconductor region on a substrate; and introducing an n-type impurity into at least a side of the fin-type semiconductor region by a plasma doping process, thereby forming an n-type impurity region in the side of the fin-type semiconductor region. In the introducing the n-type impurity, when a source power in the plasma doping process is denoted by a character Y [W], the supply of a gas containing the n-type impurity per unit time and per unit volume is set greater than or equal to 5.1×10−8/(1.72.51/24.51)×(Y/500)) [mol/(min·L·sec)], and the supply of a diluent gas per unit time and per unit volume is set greater than or equal to 1.7×10−4(202.51/24.51)×(Y/500)) [mol/(min·L·sec)].
摘要翻译： 一种制造半导体器件的方法包括：在衬底上形成翅片型半导体区域; 并且通过等离子体掺杂工艺将n型杂质引入到鳍式半导体区域的至少一侧，从而在鳍式半导体区域的侧面形成n型杂质区域。 在引入n型杂质时，当等离子体掺杂过程中的源功率由字符Y [W]表示时，每单位时间和每单位体积的含有n型杂质的气体的供给被设定为大于 或等于5.1×10-8 /（1.72.51 / 24.51）×（Y / 500））[mol /（min·L·sec）]，每单位时间和每单位体积的稀释气体供应量 大于或等于1.7×10-4（202.51 / 24.51）×（Y / 500））[mol /（min·L·sec）]]。
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公开(公告)号：US20090317963A1
公开(公告)日：2009-12-24
申请号：US12439298
申请日：2008-08-28
IPC分类号： H01L21/268
CPC分类号： H01J37/32449 , H01J37/32412 , H01J37/32935 , H01L21/2236
摘要： An amount of leakage of a substrate-cooling gas into a vacuum container is measured by using a flow-rate measuring device so that the flow rate of a diluting gas that is the same as the substrate-cooling gas is controlled by a control device or a plasma doping time is prolonged, in accordance with the amount of leakage.
摘要翻译： 通过使用流量测量装置测量基板冷却气体进入真空容器的泄漏量，使得与基板冷却气体相同的稀释气体的流量由控制装置控制或 根据泄漏量等离子体掺杂时间延长。
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公开(公告)号：US20090026540A1
公开(公告)日：2009-01-29
申请号：US12193861
申请日：2008-08-19
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7854 , H01L29/66803
摘要： A semiconductor device includes: a first semiconductor region formed on a substrate and having an upper surface and a side surface; a first impurity region of a first conductivity type formed in an upper portion of the first semiconductor region; a second impurity region of a first conductivity type formed in a side portion of the first semiconductor region; and a gate insulating film formed so as to cover at least a side surface and an upper corner of a predetermined portion of the first semiconductor region. A radius of curvature r′ of an upper corner of a portion of the first semiconductor region located outside the gate insulating film is greater than a radius of curvature r of an upper corner of a portion of the first semiconductor region located under the gate insulating film and is less than or equal to 2r.
摘要翻译： 半导体器件包括：形成在基板上并具有上表面和侧表面的第一半导体区域; 形成在第一半导体区域的上部的第一导电类型的第一杂质区; 形成在第一半导体区域的侧部的第一导电类型的第二杂质区; 以及栅极绝缘膜，其形成为覆盖所述第一半导体区域的预定部分的至少一个侧表面和上拐角。 位于栅极绝缘膜外部的第一半导体区域的一部分的上角的曲率半径r'大于栅极绝缘膜下方的第一半导体区域的一部分的上角的曲率半径r 小于等于2r。
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公开(公告)号：US08409939B2
公开(公告)日：2013-04-02
申请号：US12944224
申请日：2010-11-11
申请人： Yuichiro Sasaki , Katsumi Okashita , Bunji Mizuno
发明人： Yuichiro Sasaki , Katsumi Okashita , Bunji Mizuno
CPC分类号： H01L29/785 , H01L21/2236 , H01L29/66795
摘要： A method for fabricating a semiconductor device includes: forming a fin-type semiconductor region on a substrate; and introducing an n-type impurity into at least a side of the fin-type semiconductor region by a plasma doping process, thereby forming an n-type impurity region in the side of the fin-type semiconductor region. In the introducing the n-type impurity, when a source power in the plasma doping process is denoted by a character Y [W], the supply of a gas containing the n-type impurity per unit time and per unit volume is set greater than or equal to 5.1×10−8/((1.72.51/24.51)×(Y/500)) [mol/(min·L·sec)], and the supply of a diluent gas per unit time and per unit volume is set greater than or equal to 1.7×10−4/((202.51/24.51)×(Y/500)) [mol/(min·L·sec)].
摘要翻译： 一种制造半导体器件的方法包括：在衬底上形成翅片型半导体区域; 并且通过等离子体掺杂工艺将n型杂质引入到鳍式半导体区域的至少一侧，从而在鳍式半导体区域的侧面形成n型杂质区域。 在引入n型杂质时，当等离子体掺杂过程中的源功率由字符Y [W]表示时，每单位时间和每单位体积的含有n型杂质的气体的供给被设定为大于 或等于5.1×10-8 /（（1.72.51 / 24.51）×（Y / 500））[mol /（min·L·sec）]，并且每单位时间和每单位体积提供稀释气体 设定为大于或等于1.7×10-4 /（（202.51 / 24.51）×（Y / 500））[mol /（min·L·sec）]。
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