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1.发明授权Method for producing a semiconductor device have fin-shaped semiconductor regions 有权制造半导体器件的方法具有鳍状半导体区域公开(公告)号：US08536000B2
公开(公告)日：2013-09-17
申请号：US13185221
申请日：2011-07-18
IPC分类号： H01L21/8238 , H01L21/8234 , H01L21/336
CPC分类号： H01L29/66803 , H01L29/66795 , H01L29/7854
摘要： First and second gate insulating films are formed so as to cover at least the upper corner of first and second fin-shaped semiconductor regions. The radius of curvature r1′ of the upper corner of the first fin-shaped semiconductor region located outside the first gate insulating film is greater than the radius of curvature r1 of the upper corner of the first fin-shaped semiconductor region located under the first gate insulating film and is less than or equal to 2×r1. The radius of curvature r2′ of the upper corner of the second fin-shaped semiconductor region located outside the second gate insulating film is greater than the radius of curvature r2 of the upper corner of the second fin-shaped semiconductor region located under the second gate insulating film and is less than or equal to 2×r2.
摘要翻译： 第一和第二栅极绝缘膜形成为至少覆盖第一和第二鳍状半导体区域的上角。 位于第一栅极绝缘膜外侧的第一鳍状半导体区域的上角的曲率半径r1'大于位于第一栅极下方的第一鳍状半导体区域的上角的曲率半径r1 绝缘膜，小于或等于2×r1。 位于第二栅极绝缘膜外侧的第二鳍状半导体区域的上角的曲率半径r2'大于位于第二栅极下方的第二鳍状半导体区域的上角的曲率半径r2 绝缘膜，小于或等于2×r2。
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公开(公告)号：US20090026540A1
公开(公告)日：2009-01-29
申请号：US12193861
申请日：2008-08-19
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7854 , H01L29/66803
摘要： A semiconductor device includes: a first semiconductor region formed on a substrate and having an upper surface and a side surface; a first impurity region of a first conductivity type formed in an upper portion of the first semiconductor region; a second impurity region of a first conductivity type formed in a side portion of the first semiconductor region; and a gate insulating film formed so as to cover at least a side surface and an upper corner of a predetermined portion of the first semiconductor region. A radius of curvature r′ of an upper corner of a portion of the first semiconductor region located outside the gate insulating film is greater than a radius of curvature r of an upper corner of a portion of the first semiconductor region located under the gate insulating film and is less than or equal to 2r.
摘要翻译： 半导体器件包括：形成在基板上并具有上表面和侧表面的第一半导体区域; 形成在第一半导体区域的上部的第一导电类型的第一杂质区; 形成在第一半导体区域的侧部的第一导电类型的第二杂质区; 以及栅极绝缘膜，其形成为覆盖所述第一半导体区域的预定部分的至少一个侧表面和上拐角。 位于栅极绝缘膜外部的第一半导体区域的一部分的上角的曲率半径r'大于栅极绝缘膜下方的第一半导体区域的一部分的上角的曲率半径r 小于等于2r。
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公开(公告)号：US08063437B2
公开(公告)日：2011-11-22
申请号：US12193861
申请日：2008-08-19
IPC分类号： H01L29/66
CPC分类号： H01L29/7854 , H01L29/66803
摘要： A semiconductor device includes: a first semiconductor region formed on a substrate and having an upper surface and a side surface; a first impurity region of a first conductivity type formed in an upper portion of the first semiconductor region; a second impurity region of a first conductivity type formed in a side portion of the first semiconductor region; and a gate insulating film formed so as to cover at least a side surface and an upper corner of a predetermined portion of the first semiconductor region. A radius of curvature r′ of an upper corner of a portion of the first semiconductor region located outside the gate insulating film is greater than a radius of curvature r of an upper corner of a portion of the first semiconductor region located under the gate insulating film and is less than or equal to 2r.
摘要翻译： 半导体器件包括：形成在基板上并具有上表面和侧表面的第一半导体区域; 形成在第一半导体区域的上部的第一导电类型的第一杂质区; 形成在第一半导体区域的侧部的第一导电类型的第二杂质区; 以及栅极绝缘膜，其形成为覆盖所述第一半导体区域的预定部分的至少一个侧表面和上拐角。 位于栅极绝缘膜外部的第一半导体区域的一部分的上角的曲率半径r'大于栅极绝缘膜下方的第一半导体区域的一部分的上角的曲率半径r 小于等于2r。
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公开(公告)号：US08004045B2
公开(公告)日：2011-08-23
申请号：US12512617
申请日：2009-07-30
CPC分类号： H01L29/66803 , H01L29/66795 , H01L29/7854
摘要： First and second gate insulating films are formed so as to cover at least the upper corner of first and second fin-shaped semiconductor regions. The radius of curvature r1′ of the upper corner of the first fin-shaped semiconductor region located outside the first gate insulating film is greater than the radius of curvature r1 of the upper corner of the first fin-shaped semiconductor region located under the first gate insulating film and is less than or equal to 2×r1. The radius of curvature r2′ of the upper corner of the second fin-shaped semiconductor region located outside the second gate insulating film is greater than the radius of curvature r2 of the upper corner of the second fin-shaped semiconductor region located under the second gate insulating film and is less than or equal to 2×r2.
摘要翻译： 第一和第二栅极绝缘膜形成为至少覆盖第一和第二鳍状半导体区域的上角。 位于第一栅极绝缘膜外侧的第一鳍状半导体区域的上角的曲率半径r1'大于位于第一栅极下方的第一鳍状半导体区域的上角的曲率半径r1 绝缘膜，小于或等于2×r1。 位于第二栅极绝缘膜外侧的第二鳍状半导体区域的上角的曲率半径r2'大于位于第二栅极下方的第二鳍状半导体区域的上角的曲率半径r2 绝缘膜，小于或等于2×r2。
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公开(公告)号：US07858479B2
公开(公告)日：2010-12-28
申请号：US11596372
申请日：2005-05-12
申请人： Bunji Mizuno , Yuichiro Sasaki , Ichiro Nakayama , Hiroyuki Ito , Tomohiro Okumura , Cheng-Guo Jin , Katsumi Okashita , Hisataka Kanada
发明人： Bunji Mizuno , Yuichiro Sasaki , Ichiro Nakayama , Hiroyuki Ito , Tomohiro Okumura , Cheng-Guo Jin , Katsumi Okashita , Hisataka Kanada
IPC分类号： H01L21/8234
CPC分类号： H01L21/26513 , H01L21/26566 , H01L21/28035 , H01L29/7833
摘要： An object is to provide a semiconductor device in which uniform properties are intended and high yields are provided. Process steps are provided in which variations are adjusted in doping and annealing process steps that are subsequent process steps so as to cancel in-plane variations in a substrate caused by dry etching to finally as well provide excellent in-plane consistency in a substrate.
摘要翻译： 本发明的目的是提供一种半导体器件，其中具有均匀的性质并提供高产率。 提供了工艺步骤，其中在随后的工艺步骤的掺杂和退火工艺步骤中调整变化，以便最终消除由干蚀刻引起的衬底中的平面内变化，并且在衬底中提供优异的面内稠度。
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公开(公告)号：US20070212837A1
公开(公告)日：2007-09-13
申请号：US11596372
申请日：2005-05-12
申请人： Bunji Mizuno , Yuichiro Sasaki , Ichiro Nakayama , Hiroyuki Ito , Tomohiro Okumura , Cheng-Guo Jin , Katsumi Okashita , Hisataka Kanada
发明人： Bunji Mizuno , Yuichiro Sasaki , Ichiro Nakayama , Hiroyuki Ito , Tomohiro Okumura , Cheng-Guo Jin , Katsumi Okashita , Hisataka Kanada
IPC分类号： H01L21/77
CPC分类号： H01L21/26513 , H01L21/26566 , H01L21/28035 , H01L29/7833
摘要： An object is to provide a semiconductor device in which uniform properties are intended and high yields are provided. Process steps are provided in which variations are adjusted in doping and annealing process steps that are subsequent process steps so as to cancel in-plane variations in a substrate caused by dry etching to finally as well provide excellent in-plane consistency in a substrate.
摘要翻译： 本发明的目的是提供一种半导体器件，其中具有均匀的性质并提供高产率。 提供了工艺步骤，其中在随后的工艺步骤的掺杂和退火工艺步骤中调整变化，以便最终消除由干蚀刻引起的衬底中的平面内变化，并且在衬底中提供优异的面内稠度。
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公开(公告)号：US07800165B2
公开(公告)日：2010-09-21
申请号：US12025504
申请日：2008-02-04
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/66803 , H01L29/78621
摘要： A semiconductor region having an upper surface and a side surface is formed on a substrate. A first impurity region is formed in an upper portion of the semiconductor region. A second impurity region is formed in a side portion of the semiconductor region. The resistivity of the second impurity region is substantially equal to or smaller than that of the first impurity region.
摘要翻译： 在基板上形成具有上表面和侧面的半导体区域。 第一杂质区形成在半导体区域的上部。 第二杂质区域形成在半导体区域的侧部。 第二杂质区的电阻率基本上等于或小于第一杂质区的电阻率。
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公开(公告)号：US20090042321A1
公开(公告)日：2009-02-12
申请号：US12183775
申请日：2008-07-31
申请人： Yuichiro Sasaki , Tomohiro Okumura , Hiroyuki Ito , Keiichi Nakamoto , Katsumi Okashita , Bunji Mizuno
发明人： Yuichiro Sasaki , Tomohiro Okumura , Hiroyuki Ito , Keiichi Nakamoto , Katsumi Okashita , Bunji Mizuno
IPC分类号： H01L21/66 , C23C16/513
CPC分类号： H01J37/32449 , H01J37/32412 , H01J37/3244
摘要： Gas supplied to gas flow passages of a top plate from a gas supply device by gas supply lines forms flow along a vertical direction along a central axis of a substrate, so that the gas blown from gas blow holes can be made to be uniform, and a sheet resistance distribution is rotationally symmetric around a substrate center.
摘要翻译： 通过气体供给管线从气体供给装置供给到顶板的气体流路的气体沿着基板的中心轴线沿着垂直方向形成流动，从而能够使从气体吹入孔吹出的气体均匀， 薄片电阻分布围绕基板中心旋转对称。
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公开(公告)号：US08258585B2
公开(公告)日：2012-09-04
申请号：US12676102
申请日：2009-04-30
IPC分类号： H01L27/088
CPC分类号： H01L29/785 , H01L29/66803
摘要： A semiconductor device includes: a fin-type semiconductor region (13) formed on a substrate (11); a gate insulating film (14) formed so as to cover an upper surface and both side surfaces of a predetermined portion of the fin-type semiconductor region (13); a gate electrode (15) formed on the gate insulating film (14); and an impurity region (17) formed on both sides of the gate electrode (15) in the fin-type semiconductor region (13). An impurity blocking portion (15a) for blocking the introduction of impurities is provided adjacent both sides of the gate electrode (15) over an upper surface of the fin-type semiconductor region (13).
摘要翻译： 半导体器件包括：形成在衬底（11）上的鳍状半导体区域（13）; 形成为覆盖所述鳍状半导体区域（13）的预定部分的上表面和两个侧面的栅极绝缘膜（14）; 形成在栅极绝缘膜（14）上的栅电极（15）; 以及形成在鳍式半导体区域（13）中的栅电极（15）的两侧的杂质区域（17）。 在鳍型半导体区域（13）的上表面上，在栅电极（15）的两侧附近设置用于阻止引入杂质的杂质阻挡部（15a）。
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10.发明授权Method for producing a semiconductor device by plasma doping a semiconductor region to form an impurity region 有权通过等离子体掺杂半导体区域以形成杂质区域来制造半导体器件的方法公开(公告)号：US08105926B2
公开(公告)日：2012-01-31
申请号：US12853840
申请日：2010-08-10
IPC分类号： H01L21/425
CPC分类号： H01L29/785 , H01L29/66803 , H01L29/78621
摘要： A semiconductor region having an upper surface and a side surface is formed on a substrate. A first impurity region is formed in an upper portion of the semiconductor region. A second impurity region is formed in a side portion of the semiconductor region. The resistivity of the second impurity region is substantially equal to or smaller than that of the first impurity region.
摘要翻译： 在基板上形成具有上表面和侧面的半导体区域。 第一杂质区形成在半导体区域的上部。 第二杂质区域形成在半导体区域的侧部。 第二杂质区的电阻率基本上等于或小于第一杂质区的电阻率。
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