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    Digital to analog converter with reduced ringing
    51.
    发明申请
    Digital to analog converter with reduced ringing 失效
    数模转换器减少振铃

    公开(公告)号：US20070120717A1

    公开(公告)日：2007-05-31

    申请号：US11698954

    申请日：2007-01-29

    Applicant: Klaas Bult ,  Chi-Hung Lin

    Inventor： Klaas Bult ,  Chi-Hung Lin

    IPC: H03M1/66

    CPC classification number: H03M1/0624 ,  H03M1/0682 ,  H03M1/0872 ,  H03M1/685 ,  H03M1/747

    Abstract: Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. Each stage of the converter includes a decoder and latch arranged so the decoder inputs settle before the latch is set by the clock pulses. The stages are implemented in complementary CMOS. Complementary transistors are biased so one transistor of the pair is driven to the rail while the other transistor of the pair floats. A dummy CMOS transistor is used to balance the number of transistors in the decoder paths.

    Abstract translation: 二进制指示被转换为模拟表示，在连续的二进制指示之间的转换和每个二进制指示期间的周期中显着地减少振铃。 二进制指示以行和列矩阵布置以提供温度计代码。 转换器的每个级包括一个解码器和锁存器，所述解码器和锁存器布置成使得解码器输入在锁存器被时钟脉冲设置之前稳定。 这些阶段在互补CMOS中实现。 互补晶体管是偏置的，因此该对的一个晶体管被驱动到轨道，而另一个晶体管则浮动。 虚拟CMOS晶体管用于平衡解码器路径中的晶体管数量。

    Low noise charge pump for PLL-based frequence synthesis
    53.
    发明授权
    Low noise charge pump for PLL-based frequence synthesis 有权
    低噪声电荷泵，用于基于PLL的频率合成

    公开(公告)号：US07151413B2

    公开(公告)日：2006-12-19

    申请号：US11002497

    申请日：2004-12-02

    Applicant: Chi-Hung Lin

    Inventor： Chi-Hung Lin

    IPC: H03L7/095 ,  H03L7/24

    CPC classification number: H03L7/1974 ,  H03L7/0896 ,  H03L7/095 ,  Y10S331/02

    Abstract: A low noise charge pump for use in a PLL-based frequency synthesizer. The charge pump includes a timing controller and a plurality of charge-pump circuits. The timing controller receives a reference signal to generate a plurality of enable signals having non-overlapping phases, where the frequency of each enable signal is equal to that of the reference signal divided by the number of the enable signals. The charge-pump circuits are coupled in parallel and operate in a time-interleaved manner according to the enable signals. In response to a first and second control signal, the charge-pump circuits are able to generate respective output currents which are multiplexed together to form a charge-pump current.

    Abstract translation: 一种低噪声电荷泵，用于基于PLL的频率合成器。 电荷泵包括定时控制器和多个电荷泵电路。 定时控制器接收参考信号以产生具有非重叠相位的多个使能信号，其中每个使能信号的频率等于参考信号的频率除以使能信号的数目。 电荷泵电路并联耦合并根据使能信号以时间交替的方式工作。 响应于第一和第二控制信号，电荷泵电路能够产生被多路复用在一起以形成电荷泵电流的各自的输出电流。

    Aquarium filter having self-priming arrangement
    56.
    发明授权
    Aquarium filter having self-priming arrangement 失效
    水族箱过滤器具有自吸排列

    公开(公告)号：US07001509B1

    公开(公告)日：2006-02-21

    申请号：US10938344

    申请日：2004-09-09

    Applicant: Chi-Hung Lin

    Inventor： Chi-Hung Lin

    IPC: A01K63/04

    CPC classification number: A01K63/045

    Abstract: An external aquarium filter comprises a flow resistive, porous member disposed between a partition wall and the filter housing. Responsive to stopping the pump, water in the intake chamber begins to reversely flow out of the intake chamber into the aquarium tank through the intake tube due to siphoning, water in the filtering chamber flows back to the intake chamber through the porous member, the reverse flow is faster than water flowing into the intake chamber such that the siphoning breaks when the water level of the intake chamber drops below that of the filtering chamber, the water in the filtering chamber continues to flow back to the intake chamber through the porous member until both the filtering chamber and the intake chamber have the same water level, and sufficient priming water is thus stored in the intake chamber for a future restarting of the filter.

    Abstract translation: 外部水族箱过滤器包括设置在分隔壁和过滤器壳体之间的阻流多孔构件。 响应于停止泵，吸入室中的水由于虹吸而开始通过进气管从进气室反向流出到水族箱中，过滤室中的水通过多孔构件流回到进气室，反向 流动比进入进气室的水快，使得当进气室的水位低于过滤室的水位时虹吸断裂，过滤室中的水通过多孔构件继续流回到进气室直到 过滤室和进气室都具有相同的水位，因此足够的起动水储存在进气室中，以便将来重新启动过滤器。

    Single-ended-to-differential converter with common-mode voltage control
    57.
    发明申请
    Single-ended-to-differential converter with common-mode voltage control 有权

    公开(公告)号：US20050140446A1

    公开(公告)日：2005-06-30

    申请号：US11060395

    申请日：2005-02-17

    Applicant: Jan Mulder ,  Marcel Lugthart ,  Chi-Hung Lin

    Inventor： Jan Mulder ,  Marcel Lugthart ,  Chi-Hung Lin

    IPC: H03H11/32 ,  H03F3/45

    CPC classification number: H03H11/32

    Abstract: Provided is a circuit to perform single-ended to differential conversion while providing common-mode voltage control. The circuit includes a converter to convert a single-ended signal to a differential signal and a stabilizing circuit adapted to receive the differential signal. The stabilizing circuit includes a sensor configured to sense a common-mode voltage level of the differential signal and a comparator having an output port coupled to the converter. The comparator is configured to compare the differential signal common-mode voltage level with a reference signal common-mode voltage level and produce an adjusting signal based upon the comparison. The adjusting signal is applied to the converter via the output port and is operative to adjust a subsequent common-mode voltage level of the differential signal.

    Single-ended-to-differential converter with common-mode voltage control
    59.
    发明授权
    Single-ended-to-differential converter with common-mode voltage control 有权
    具有共模电压控制的单端到差分转换器

    公开(公告)号：US06771127B2

    公开(公告)日：2004-08-03

    申请号：US10105253

    申请日：2002-03-26

    Applicant: Jan Mulder ,  Marcel Lugthart ,  Chi-Hung Lin

    Inventor： Jan Mulder ,  Marcel Lugthart ,  Chi-Hung Lin

    IPC: H03F345

    CPC classification number: H03H11/32

    Abstract: Provided is a circuit to perform single-ended to differential conversion while providing common-mode voltage control. The circuit includes a converter to convert a single-ended signal to a differential signal and a stabilizing circuit adapted to receive the differential signal. The stabilizing circuit includes a sensor configured to sense a common-mode voltage level of the differential signal and a comparator having an output port coupled to the converter. The comparator is configured to compare the differential signal common-mode voltage level with a reference signal common-mode voltage level and produce an adjusting signal based upon the comparison. The adjusting signal is applied to the converter via the output port and is operative to adjust a subsequent common-mode voltage level of the differential signal.

    Abstract translation: 提供了在提供共模电压控制的同时执行单端到差分转换的电路。 电路包括将单端信号转换为差分信号的转换器和适于接收差分信号的稳定电路。 稳定电路包括被配置为感测差分信号的共模电压电平的传感器和具有耦合到转换器的输出端口的比较器。 比较器被配置为将差分信号共模电压电平与参考信号共模电压电平进行比较，并且基于该比较产生调整信号。 调整信号经由输出端口被施加到转换器，并且可操作地调整差分信号的后续共模电压电平。

    Digital to analog converter with reduced ringing
    60.
    发明授权
    Digital to analog converter with reduced ringing 有权
    数模转换器减少振铃

    公开(公告)号：US06714150B2

    公开(公告)日：2004-03-30

    申请号：US10320016

    申请日：2002-12-16

    Applicant: Klaas Bult ,  Chi-Hung Lin

    Inventor： Klaas Bult ,  Chi-Hung Lin

    IPC: H03M166

    CPC classification number: H03M1/0624 ,  H03M1/0682 ,  H03M1/0872 ,  H03M1/685 ,  H03M1/747

    Abstract: Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. Each stage of the converter includes a decoder and latch arranged so the decoder inputs settle before the latch is set by the clock pulses. The stages are implemented in complementary CMOS. Complementary transistors are biased so one transistor of the pair is driven to the rail while the other transistor of the pair floats. A dummy CMOS transistor is used to balance the number of transistors in the decoder paths.

    Abstract translation: 二进制指示被转换为模拟表示，在连续的二进制指示之间的转换和每个二进制指示期间的周期中显着地减少振铃。 二进制指示以行和列矩阵布置以提供温度计代码。 转换器的每个级包括一个解码器和锁存器，所述解码器和锁存器被布置成使得解码器输入在锁存器被时钟脉冲设置之前稳定。 这些阶段在互补CMOS中实现。 互补晶体管是偏置的，因此该对的一个晶体管被驱动到轨道，而另一个晶体管则浮动。 虚拟CMOS晶体管用于平衡解码器路径中的晶体管数量。

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