公开(公告)号：US07058784B2

公开(公告)日：2006-06-06

申请号：US10604247

申请日：2003-07-04

Applicant: Chih-Hung Wang

Inventor： Chih-Hung Wang

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/2022 ,  G06F2212/7202 ,  G06F2212/7203

Abstract: A method for managing the access procedure for large block flash memory by employing a page cache block, so as to reduce the occurrence of swap operation is proposed. At least one block of the nonvolatile memory is used as a page cache block. When a host requests to write a data to storage device, the last page of the data is written into one available page of the page cache block by the controller. A block structure is defined in the controller having a data block for storing original data, a writing block for temporary data storage in the access operation, and a page cache block for storing the last one page data to be written.

Abstract translation: 提出了一种通过采用页面缓存块来管理大块闪存的访问过程的方法，以便减少交换操作的发生。 非易失性存储器的至少一个块被用作页面高速缓存块。 当主机请求将数据写入存储设备时，数据的最后一页由控制器写入页面缓存块的一个可用页面。 在具有用于存储原始数据的数据块，用于访问操作中的临时数据存储的写入块和用于存储要写入的最后一页数据的页面高速缓存块的控制器中定义了块结构。

公开(公告)号：US20060050314A1

公开(公告)日：2006-03-09

申请号：US11216215

申请日：2005-09-01

Applicant: Hitoshi Shiga ,  Chih-Chung Chen ,  Chih-Hung Wang ,  Sheng-Lin Hung

Inventor： Hitoshi Shiga ,  Chih-Chung Chen ,  Chih-Hung Wang ,  Sheng-Lin Hung

IPC: G06K15/00

CPC classification number: G11C16/102 ,  G11C16/0483 ,  G11C16/26 ,  G11C2207/2236 ,  G11C2216/14

Abstract: A memory system includes a memory cell array, a bit line switch, first and second page buffers, a column switch, an error correction circuit, and control circuits. The second page buffer can swap data with the first page buffer. The control circuits controls the bit line switch and the first and second page buffers, sequentially reads, page by page, one or more pages from the mth (m is a positive integer) page to the nth (n is an integer greater than m) page of the first block in the memory cell array, controls the error correction circuit to perform error correction calculation by the error correction circuit, controls the first and second data buffers and the bit line switch, and controls to perform write in the second block in the erase state in the memory cell array.

Abstract translation: 存储器系统包括存储单元阵列，位线开关，第一和第二页缓冲器，列开关，纠错电路和控制电路。 第二页缓冲区可以与第一页缓冲区交换数据。 控制电路控制位线开关，第一和第二页缓冲器逐页依次读取从第m（m为正整数）页到第n（n为大于m的整数）的一页或多页， 控制误差校正电路进行误差校正电路的误差校正计算，控制第一和第二数据缓冲器和位线开关，并控制在第二块中执行写入 存储单元阵列中的擦除状态。

公开(公告)号：US20050169053A1

公开(公告)日：2005-08-04

申请号：US11096997

申请日：2005-03-31

Applicant: Chun-Hung Lin ,  Chih-Hung Wang ,  Chun-Hao Kuo

Inventor： Chun-Hung Lin ,  Chih-Hung Wang ,  Chun-Hao Kuo

IPC: G06F12/06 ,  G06F11/16 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F13/00 ,  G11C7/10 ,  G11C11/34 ,  G11C16/00 ,  G11C16/06 ,  G11C29/00

CPC classification number: G06F12/0246 ,  G06F11/1068 ,  G06F11/1435 ,  G06F12/0292 ,  G06F2212/7203

Abstract: A window-based flash memory storage system and a management and an access method therefor are proposed. The window-based flash memory storage system includes a window-based region and a redundant reserved region; wherein the window-based region is used to store a number of windows, each window being associated with a number of physical blocks. The redundant reserved region includes a dynamic-link area, a window-information area, a dynamic-link information area, and an boot-information area; wherein the dynamic-link area includes a plurality of dynamic allocation blocks, each being allocatable to any window. The window-information area is used to store a specific window-information set that is dedicated to a certain window within a specific range of data storage space. The dynamic-link information area is used to record the status of the allocation of the dynamic allocation blocks to the windows.

Abstract translation: 提出了一种基于窗口的闪存存储系统及其管理和访问方法。 基于窗口的闪存存储系统包括基于窗口的区域和冗余保留区域; 其中基于窗口的区域用于存储多个窗口，每个窗口与多个物理块相关联。 冗余保留区域包括动态链路区域，窗口信息区域，动态链路信息区域和引导信​​息区域; 其中所述动态链接区域包括多个动态分配块，每个动态分配块可分配给任何窗口。 窗口信息区域用于存储专用于数据存储空间的特定范围内的特定窗口的特定窗口信息集。 动态链接信息区域用于将动态分配块的分配状态记录到窗口。

公开(公告)号：US06734127B2

公开(公告)日：2004-05-11

申请号：US09973524

申请日：2001-10-09

Applicant: Dong-Hau Kuo ,  Chih-Hung Wang

Inventor： Dong-Hau Kuo ,  Chih-Hung Wang

IPC: C04B35468

CPC classification number: H01G4/1227 ,  C04B35/4682 ,  C04B35/4684 ,  C04B35/64 ,  C04B35/645 ,  C04B2235/3206 ,  C04B2235/3213 ,  C04B2235/3227 ,  C04B2235/3251 ,  C04B2235/36 ,  C04B2235/663 ,  C04B2235/785 ,  C04B2235/786 ,  C04B2235/96

Abstract: The present invention discloses low-cost ceramic powders prepared by the conventional ceramic processing with ceramic raw materials comprising carbonates, oxides and/or hydroxides of barium (Ba), titanium (Ti), magnesium (Mg) and optionally strontium (Sr), lanthanum (La) and niobium (Nb), and lead titanate (PbTiO3) and/or lead oxide (PbO). The present invention also discloses a ceramic material obtained by the ceramic powder through densification and reduction-reoxidation, which has a dielectric constant of about 20,000 to about 55,000, a dielectric loss tangent (tan &dgr;) of about 0.05 to about 0.25, a low capacitance change with temperature (low TCC) of about −15% to about 10% at a temperature range of −55° C. to 150° C., a resistivity of about 106 &OHgr;·cm to about 109 &OHgr;·cm, and a small grain size of about 0.5 to about 3.5 &mgr;m. The ceramic materials are useful in the production of capacitors or modules having high performance such as high dielectric constants and low TCC values with low cost. The ceramic powder also can mix with a glass component of low melting temperature to form a low temperature co-fired capacitor.

Abstract translation: 本发明公开了通过常规陶瓷处理制备的低成本陶瓷粉末，其中陶瓷原料包括钡（Ba），钛（Ti），镁（Mg）和任选的锶（Sr），镧的碳酸盐，氧化物和/或氢氧化物 （La）和铌（Nb），以及钛酸铅（PbTiO 3）和/或氧化铅（PbO）。 本发明还公开了通过致密化和还原 - 再氧化获得的陶瓷材料，其具有约20,000至约55,000的介电常数，介电损耗角正切（tanδ）为约0.05至约0.25，低电容 在-55℃至150℃的温度范围内随温度（低TCC）变化约-15％至约10％，电阻率为约10 -6Ω〜约10 9Ω cm，小粒径约0.5-3.5μm。 陶瓷材料可用于生产具有高性能的电容器或模块，例如高介电常数和低成本的低TCC值。 陶瓷粉末也可以与低熔点玻璃组分混合形成低温共烧电容器。