摘要:
A multi-port memory device with an array of single-port memory cells is disclosed. According to one embodiment of the invention, the multi-port memory device has N number of memory ports, and is capable of performing any combination of N number of read/write operations during a single cycle of an externally generated core clock signal, without the need of any other externally generated clocking signals.
摘要:
Error checking and correcting (ECC) is performed on data held in a content addressable memory. An error check circuit receives words from a memory circuit or circuits, generates an error status and generates a corrected value when appropriate. A control circuit sequences through each of the words of the memory circuit(s), periodically reads from the memory circuit the next word in the sequence and provides the next word to the error check circuit. The bandwidth consumed by the periodic error check phase can be controlled by adjusting the interval between reads.
摘要:
Apparatus, methods, and systems are disclosed for providing a memory device, such as a SDRAM, having distributed memory bank segments logically coupled to form a virtual memory bank. Each of the memory bank segments are proximally positioned relative to associated I/Os. In this way, the delay times from each of the memory bank segments to their respective I/Os are substantially equal to each other. In addition, the proximal positioning of the memory banks results in reduced signal delays due to reduced signal paths from each bank segment and respective I/O.
摘要:
A system and/or method for simultaneous read/write access of 1-Transistor (1-T) dynamic random access memory (DRAM), which does not rely on a dual-port DRAM to perform read and write accesses within single clock cycle. A single-port 1-T DRAM works with modified design of read sense amplifier to perform both read and write accesses within single clock cycle, thereby retaining high performance and compact size that characterize the 1-T DRAM while allowing simultaneous read/write access that characterizes dual-port memory. Hence, single-port 1-T DRAM constitutes a pseudo dual-port 1-T DRAM that emulates the dual-port DRAM's ability in performing simultaneous read/write memory access of 1-T DRAM.
摘要:
An SRAM array configuration is disclosed. SRAM cells (102) are arranged in rows and columns. Cell rows (104a-104f) are each driven by a particular word line (132). Cell row pairs (108a and 108b) are supplied with a low power supply voltage (Vss) by a number of Vss connections 116 disposed parallel to the cell rows (104a-104f). The word lines (132) and Vss connections 116 are "strapped" by low resistance word line straps (110b-110e) and Vss straps (112a-112b). Both the word line straps (110b-110e) and the Vss straps (112a-112b) are substantially offset with respect to their associated word lines (132) and Vss connections 116, respectively. The Vss strap offset is accomplished with the use of a Vss line 140 that makes contact with the Vss connections 116 and further includes landing portions 120 which extend in the column direction and make contact with the Vss straps (112a-112b).
摘要:
A random access memory (RAM) (10) is disclosed. A network of driver lines (28) extends over a number of core arrays (12a-12p) connecting a control bank 24 with column decode banks (26a and 26b), and the column decode banks (26a and 26b) with sense banks 46 within the core arrays (12a-12p). The driver lines 28 include predecode lines 30 and clock lines 32 for coupling predecode signals and clock signals from the control bank 24 to the column decode banks (26a and 26b). In addition, the driver lines 28 include column select lines 34 and sense driver lines 36 for coupling column select signals and sense amplifier enable signals from the column decode banks (26a and 26b) to the sense banks 46. The sense banks 46 include sense amplifiers 80 that are shared between array quadrants 42 by decoded transfer gate banks (70a and 70b). Advantageous placement of precharge circuits 82 and equalization circuits 86 provides a compact sense bank structure 46.