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公开(公告)号：US20060238528A1
公开(公告)日：2006-10-26
申请号：US11384101
申请日：2006-03-17
IPC: G09G5/00
CPC classification number: G09G3/22 , G09G3/2014 , G09G2310/0254 , G09G2310/027 , G09G2330/021
Abstract: A driving apparatus and a driving method for an electron emission device include a polarity operator for receiving an external video data signal and a horizontal synchronization signal, and generating a polarity control signal in response to the horizontal synchronization signal. The apparatus further includes a data inverter for selectively inverting video data output from the polarity operator, a serial-parallel converter for converting video data output from the data inverter into parallel data, a pulse width modulator for modulating a pulse width of the parallel data output from the serial-parallel converter, and a polarity controller for selectively inverting a signal output from the pulse width modulator.
Abstract translation: 电子发射装置的驱动装置和驱动方法包括用于接收外部视频数据信号和水平同步信号的极性运算器，并且响应于水平同步信号产生极性控制信号。 该装置还包括用于选择性地反转从极性运算器输出的视频数据的数据反相器，将从数据反相器输出的视频数据转换成并行数据的串并联转换器，用于调制并行数据输出的脉冲宽度的脉宽调制器 串行并行转换器和用于选择性地反相从脉冲宽度调制器输出的信号的极性控制器。
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52.发明申请Semiconductor devices having buried bit lines and methods of manufacturing semiconductor devices having buried bit lines 失效具有掩埋位线的半导体器件和具有掩埋位线的半导体器件的制造方法公开(公告)号：US20060131613A1
公开(公告)日：2006-06-22
申请号：US11240544
申请日：2005-09-30
Applicant: Tae-yong Kim , Choong-ho Lee , Chul Lee , Eun-suk Cho , Suk-kang Sung , Hye-jin Cho
Inventor： Tae-yong Kim , Choong-ho Lee , Chul Lee , Eun-suk Cho , Suk-kang Sung , Hye-jin Cho
IPC: H01L27/10
CPC classification number: H01L27/115 , H01L27/11568
Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type and having an upper portion, a pair of bit lines extending in a first direction and doped with an impurity of a second conductivity type opposite to the first conductivity type and spaced from one another in the upper portion of the semiconductor substrate, a first line formed between the pair of bit lines having a plurality of alternating recessed device isolation regions and channel regions, with each of the channel regions contacting each bit line of the at least one pair of bit lines, and word lines formed at right angles to the first lines and covering the channel regions.
Abstract translation: 半导体器件包括具有第一导电类型并具有上部的半导体衬底，一对位线沿着第一方向延伸并且掺杂有与第一导电类型相反并且彼此间隔开的第二导电类型的杂质 所述半导体衬底的上部，形成在所述一对位线之间的第一线，所述第一线具有多个交替的凹陷器件隔离区域和沟道区域，其中每个沟道区域与所述至少一对位线的每个位线接触 以及与第一线成直角形成并覆盖沟道区的字线。
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53.发明申请Semiconductor memory devices including a vertical channel transistor and methods of manufacturing the same 有权包括垂直沟道晶体管的半导体存储器件及其制造方法公开(公告)号：US20060097304A1
公开(公告)日：2006-05-11
申请号：US11151673
申请日：2005-06-13
Applicant: Jae-man Yoon , Dong-gun Park , Choong-ho Lee , Moon-suk Yi , Chul Lee
Inventor： Jae-man Yoon , Dong-gun Park , Choong-ho Lee , Moon-suk Yi , Chul Lee
CPC classification number: H01L27/10885 , H01L27/0207 , H01L27/10814 , H01L27/10876 , H01L29/66666
Abstract: Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain region is in an upper portion of at least one of the adjacent pillars. A buried bit line is in the first source/drain region and electrically coupled to the first source/drain region and a storage node electrode is on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region.
Abstract translation: 半导体存储器件包括在半导体衬底上具有间隔关系的半导体衬底和多个半导体材料柱。 相邻的围绕电极围绕其中的一个柱。 第一源极/漏极区域在相邻的柱之间的半导体衬底中，并且第二源极/漏极区域位于至少一个相邻支柱的上部。 掩埋位线在第一源极/漏极区域中并且电耦合到第一源极/漏极区域，并且存储节点电极在相邻柱的至少一个的上部上并且与第二源极/漏极 地区。
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公开(公告)号：US20060017104A1
公开(公告)日：2006-01-26
申请号：US11183997
申请日：2005-07-19
Applicant: Jae-Man Yoon , Dong-Gun Park , Choong-Ho Lee , Chul Lee
Inventor： Jae-Man Yoon , Dong-Gun Park , Choong-Ho Lee , Chul Lee
CPC classification number: H01L29/78696 , H01L29/66666 , H01L29/66772 , H01L29/78642
Abstract: A semiconductor device may include a tubular channel pattern vertically extending from a semiconductor substrate. A gate insulation layer may be provided on faces exposed through the channel pattern. A gate electrode may be provided on the gate insulation layer. The gate electrode may fill the channel pattern. A conductive region, which may serve as lower source/drain regions, may be formed at a surface portion of the semiconductor substrate. The conductive region may contact a lower portion of the channel pattern. A conductive pattern, which may serve as upper source/drain regions, may horizontally extend from an upper portion of the channel pattern.
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公开(公告)号：US09836226B2
公开(公告)日：2017-12-05
申请号：US15000065
申请日：2016-01-19
Applicant: Young-Ho Park , Chan-Ik Park , Chul Lee , In-Hwan Doh , Nam-Wook Kang , Kwang-Hun Lee , In-Sung Song
Inventor： Young-Ho Park , Chan-Ik Park , Chul Lee , In-Hwan Doh , Nam-Wook Kang , Kwang-Hun Lee , In-Sung Song
IPC: G06F3/06
CPC classification number: G06F3/0611 , G06F3/0659 , G06F3/0679
Abstract: A method of processing input/output (I/O) in a storage device includes adjusting a read anticipation time based on a change of a resource management status related to operations of the storage device and performing an I/O processing operation at the storage device based on the adjusted read anticipation time. The I/O processing operation is performed to postpone an operation regarding a program command and perform a read command at higher priority than a write command at the storage device in a period from completion of a read operation at the storage device until the read anticipation time has elapsed.
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Patent Agency Ranking
56.发明授权Methods of forming semiconductor devices to include single body interconnection patterns using fine patterning techniques, and semiconductor device so formed 有权使用精细图案形成技术形成半导体器件以包括单体互连图案的方法，以及如此形成的半导体器件公开(公告)号：US09590034B2
公开(公告)日：2017-03-07
申请号：US14682132
申请日：2015-04-09
Applicant: Seok-ho Shin , Chul Lee
Inventor： Seok-ho Shin , Chul Lee
IPC: H01L29/06 , H01L27/02 , H01L27/108 , H01L21/768
CPC classification number: H01L29/0649 , H01L21/3086 , H01L21/32139 , H01L21/76816 , H01L21/76895 , H01L27/0207 , H01L27/10814 , H01L27/10885 , H01L27/10894
Abstract: A method of forming fine patterns for a semiconductor device includes providing a substrate with a first region and a second region, forming a conductive layer on the substrate, the conductive layer including a plate portion covering the first region and first protruding portions extending from the plate portion in a first direction and covering a portion of the second region, forming first mask patterns on the conductive layer, the first mask patterns extending in the first direction and being spaced apart from each other in a second direction crossing the first direction, forming a second mask pattern on the second region to cover the first protruding portions, and patterning the conductive layer using the first and second mask patterns as an etch mask to form conductive patterns. In plan view, each of the first protruding portions is overlapped with a corresponding one of the first mask patterns.
Abstract translation: 一种形成半导体器件的精细图案的方法包括：提供具有第一区域和第二区域的衬底，在衬底上形成导电层，所述导电层包括覆盖第一区域的板部分和从板延伸的第一突出部分 部分在第一方向上并且覆盖第二区域的一部分，在导电层上形成第一掩模图案，第一掩模图案沿第一方向延伸并且在与第一方向交叉的第二方向上彼此间隔开，形成 在第二区域上的第二掩模图案，以覆盖第一突出部分，并且使用第一和第二掩模图案将导电层图案化为蚀刻掩模以形成导电图案。 在平面图中，每个第一突出部分与第一掩模图案中的相应一个重叠。
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公开(公告)号：US09158475B2
公开(公告)日：2015-10-13
申请号：US12771203
申请日：2010-04-30
Applicant: Seung-woo Ryu , Jae-min Ryu , Chul Lee
Inventor： Seung-woo Ryu , Jae-min Ryu , Chul Lee
CPC classification number: G06F3/0679 , G06F11/1441 , G06F13/1694
Abstract: A memory apparatus and an operation of the memory apparatus which allow quick booting are provided. The memory apparatus includes a volatile memory, a non-volatile memory, and a memory control unit to control input/output of data stored in the volatile memory and the non-volatile memory. The memory control unit restores data, according to a control command input from outside of the memory apparatus, from the non-volatile memory to the volatile memory in an on-demand fashion during booting.
Abstract translation: 提供了允许快速启动的存储装置和存储装置的操作。 存储装置包括易失性存储器，非易失性存储器和存储器控制单元，用于控制存储在易失性存储器和非易失性存储器中的数据的输入/输出。 存储器控制单元根据从存储装置外部输入的控制命令，在引导期间按照需要将数据从非易失性存储器恢复到易失性存储器。
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公开(公告)号：US08438195B2
公开(公告)日：2013-05-07
申请号：US13304579
申请日：2011-11-25
Applicant: Jae Geuk Kim , Chul Lee , Joo Young Hwang
Inventor： Jae Geuk Kim , Chul Lee , Joo Young Hwang
IPC: G06F7/00
CPC classification number: G06F17/30129
Abstract: A method of operating a file system in a host configured to store write data in a data storage device including a first region and a second region is disclosed, and includes; receiving a write data request for write data associated with a file, classifying the write data as hot data or cold data using file meta data for the file, and if the write data is classified as hot data, storing the write data in the first region, and otherwise if the write data is classified as cold data storing the write data in the second region.
Abstract translation: 公开了一种在被配置为将写入数据存储在包括第一区域和第二区域的数据存储设备中的主机中操作文件系统的方法，并且包括： 接收与文件相关联的写入数据的写入数据请求，使用文件的文件元数据将写入数据分类为热数据或冷数据，并且如果写入数据被分类为热数据，则将写入数据存储在第一区域 ，否则如果写入数据被分类为在第二区域中存储写入数据的冷数据。
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公开(公告)号：US20120209893A1
公开(公告)日：2012-08-16
申请号：US13304579
申请日：2011-11-25
Applicant: Jae Geuk Kim , Chul Lee , Joo Young Hwang
Inventor： Jae Geuk Kim , Chul Lee , Joo Young Hwang
IPC: G06F17/30
CPC classification number: G06F17/30129
Abstract: A method of operating a file system in a host configured to store write data in a data storage device including a first region and a second region is disclosed, and includes; receiving a write data request for write data associated with a file, classifying the write data as hot data or cold data using file meta data for the file, and if the write data is classified as hot data, storing the write data in the first region, and otherwise if the write data is classified as cold data storing the write data in the second region.
Abstract translation: 公开了一种在被配置为将写入数据存储在包括第一区域和第二区域的数据存储设备中的主机中操作文件系统的方法，并且包括： 接收与文件相关联的写入数据的写入数据请求，使用文件的文件元数据将写入数据分类为热数据或冷数据，并且如果写入数据被分类为热数据，则将写入数据存储在第一区域 ，否则如果写入数据被分类为在第二区域中存储写入数据的冷数据。
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60.发明授权Semiconductor memory devices including a vertical channel transistor having a buried bit line 有权半导体存储器件包括具有埋入位线的垂直沟道晶体管公开(公告)号：US08154065B2
公开(公告)日：2012-04-10
申请号：US12418879
申请日：2009-04-06
Applicant: Jae-man Yoon , Dong-gun Park , Choong-ho Lee , Moon-suk Yi , Chul Lee
Inventor： Jae-man Yoon , Dong-gun Park , Choong-ho Lee , Moon-suk Yi , Chul Lee
IPC: H01L27/108
CPC classification number: H01L27/10885 , H01L27/0207 , H01L27/10814 , H01L27/10876 , H01L29/66666
Abstract: Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain region is in an upper portion of at least one of the adjacent pillars. A buried bit line is in the first source/drain region and electrically coupled to the first source/drain region and a storage node electrode is on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region.
Abstract translation: 半导体存储器件包括在半导体衬底上具有间隔关系的半导体衬底和多个半导体材料柱。 相邻的围绕电极围绕其中的一个柱。 第一源极/漏极区域在相邻的柱之间的半导体衬底中，并且第二源极/漏极区域位于至少一个相邻支柱的上部。 掩埋位线在第一源极/漏极区域中并且电耦合到第一源极/漏极区域，并且存储节点电极在相邻柱的至少一个的上部上并且与第二源极/漏极 地区。
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