公开(公告)号：US06914299B2

公开(公告)日：2005-07-05

申请号：US10437092

申请日：2003-05-13

Applicant: Chung-Cheng Wu

Inventor： Chung-Cheng Wu

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L27/01 ,  H01L27/12 ,  H01L29/76 ,  H01L29/94 ,  H01L31/0392

CPC classification number: H01L29/42392 ,  H01L29/0657 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/78654 ,  H01L29/78696

Abstract: A horizontal surrounding gate MOSFET comprises a monolithic structure formed in an upper silicon layer of a semiconductor substrate which is essentially a silicon-on-insulator (SOI) wafer, the monolithic structure comprising a source and drain portion oppositely disposed on either end of a cylindrical channel region longitudinally disposed between the source and drain. The channel is covered with a gate dielectric and an annular gate electrode is formed circumferentially covering the channel.

Abstract translation: 水平周围栅极MOSFET包括形成在半导体衬底的上硅层中的整体结构，其基本上是绝缘体上硅（SOI）晶片，所述整体结构包括相对地设置在圆柱形 通道区域纵向设置在源极和漏极之间。 通道被栅极电介质覆盖，并且环形栅电极沿周向覆盖通道。

公开(公告)号：US20050012173A1

公开(公告)日：2005-01-20

申请号：US10619114

申请日：2003-07-14

Applicant: Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

Inventor： Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

IPC: H01L21/762 ,  H01L21/8234 ,  H01L21/76 ,  H01L21/337 ,  H01L29/00

CPC classification number: H01L21/823481 ,  H01L21/26586 ,  H01L21/76237

Abstract: A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the top of the substrate to expose the top portion of the oxide liner. An angled indium implant through the oxide liner into the substrate is then performed. The plug is removed and an insulator is deposited to fill the trenches. After planarization and wet etch steps, formation of a gate dielectric layer and a patterned gate layer, the NMOS transistor exhibits an improved Vt roll-off of 40 to 45 mVolts for both long and short channels. The improvement is achieved with no degradation in junction or isolation performance. The indium implant dose and angle may be varied to provide flexibility to the process.

Abstract translation: 描述了一种在NMOS晶体管中减小反向窄宽度效应的方法。 氧化物衬垫沉积在形成为隔离衬底中的有源区域的浅沟槽中。 在浅沟槽中形成光致抗蚀剂插塞，并且在衬底的顶部下方凹入以暴露氧化物衬垫的顶部部分。 然后进行通过氧化物衬垫到衬底中的成角度的铟植入物。 去除插头并沉积绝缘体以填充沟槽。 在平坦化和湿蚀刻步骤之后，形成栅极介电层和图案化栅极层，NMOS晶体管对于长沟道和短沟道都表现出改善的Vt滚降为40至45毫伏。 在不会降低结或隔离性能的情况下实现改进。 可以改变铟注入剂量和角度以提供该过程的灵活性。

公开(公告)号：US06789564B1

公开(公告)日：2004-09-14

申请号：US10426634

申请日：2003-05-01

Applicant: Chung-Cheng Wu

Inventor： Chung-Cheng Wu

IPC: F16L500

CPC classification number: B65H75/4463 ,  B65H75/38 ,  B65H2701/33 ,  F16L3/012 ,  Y10T137/598 ,  Y10T137/6921 ,  Y10T137/6954 ,  Y10T137/698

Abstract: A hose reel includes a reel and a movable curve tube disposed on the center of a tabular rack. A cover is fixed on a lateral side of the rack while a crank is positioned on the other lateral side. A multi-path hose connects to a movable curve tube by a coupling for being wound on the reel through the crank. Thus the hose is pulled out at the desired length for easy use and ideal storage

Abstract translation: 软管卷轴包括设置在平板状架的中心的卷轴和可动曲线管。 盖子固定在齿条的侧面上，而曲柄位于另一侧面。 多通道软管通过联接器连接到可动弯管，用于通过曲柄缠绕在卷轴上。 因此，软管以期望的长度拉出以便于使用和理想的储存

公开(公告)号：US6133597A

公开(公告)日：2000-10-17

申请号：US900560

申请日：1997-07-25

Applicant: Li-Chun Li ,  Huoy-Jong Wu ,  Chung-Cheng Wu ,  Saysamone Pittikoun ,  Wen-Wei Lo

Inventor： Li-Chun Li ,  Huoy-Jong Wu ,  Chung-Cheng Wu ,  Saysamone Pittikoun ,  Wen-Wei Lo

IPC: H01L21/761 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L27/10894 ,  H01L21/761 ,  H01L21/76202 ,  H01L27/10897

Abstract: Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order to block the channels stop implant from an N+ contact region used for DNW biasing. In DRAMs and other integrated circuits, a minimal spacing requirement between a well of an integrated circuit on the one hand and adjacent circuitry on the other hand is eliminated by laying out the adjacent circuitry so that the well is located adjacent to a transistor having an electrode connected to the same voltage as the voltage that biases the well. For example, in DRAMs, the minimal spacing requirement between the DNW and the read/write circuitry is eliminated by locating the DNW next to a transistor precharging the bit lines before memory accesses. One electrode of the transistor is connected to a precharge voltage. This electrode overlaps the DNW which is biased to the same precharge voltage. This electrode provides the DNW N+ contact region.

Abstract translation: 动态随机存取存储器（DRAM）单元形成在偏置深N阱（DNW）中形成的P阱中。 在N个阱中形成PMOS晶体管。 NMOS通道停止注入掩模被修改为不是N阱掩模的反向，以阻止通道从用于DNW偏置的N +接触区域停止注入。 在DRAM和其他集成电路中，通过布置相邻电路来消除一方面集成电路的阱与另一方面的相邻电路之间的最小间隔要求，使得阱位于与具有电极的晶体管相邻的位置 连接到与电压偏压相同的电压。 例如，在DRAM中，通过将存储器访问之前的位线预先充电的晶体管旁边的DNW定位在DNW和读/写电路之间的最小间隔要求被消除。 晶体管的一个电极连接到预充电电压。 该电极与被偏置到相同预充电电压的DNW重叠。 该电极提供DNW N +接触区域。

公开(公告)号：US5895945A

公开(公告)日：1999-04-20

申请号：US791596

申请日：1997-01-31

Applicant: Hong-Tsz Pan ,  Chung-Cheng Wu ,  Ming-Tzong Yang

Inventor： Hong-Tsz Pan ,  Chung-Cheng Wu ,  Ming-Tzong Yang

IPC: H01L21/8247 ,  H01L27/108

CPC classification number: H01L27/11521 ,  H01L27/11558

Abstract: A MOSFET device with a substrate covered with dielectric material with the device including a plurality of buried conductors capacitively coupled to a polysilicon electrode, made by the steps comprisingforming between regions containing MOSFET devices a region with a plurality of bit lines in the substrate by ion implantation through the gate oxide into the substrate in a predetermined pattern and,forming a polysilicon electrode on the dielectric material crossing over the bit lines.

Abstract translation: 一种具有被绝缘材料覆盖的衬底的MOSFET器件，该器件包括电容耦合到多晶硅电极的多个掩埋导体，所述多个掩埋导体通过以下步骤形成，所述步骤包括：在包含MOSFET器件的区域之间形成具有衬底中的多个位线的区域， 以预定图案将栅极氧化物注入到衬底中，并且在穿过位线的电介质材料上形成多晶硅电极。

公开(公告)号：US5541876A

公开(公告)日：1996-07-30

申请号：US251972

申请日：1994-06-01

Applicant: Chen-Chin Hsue ,  Ming-Tzong Yang ,  Chung-Cheng Wu

Inventor： Chen-Chin Hsue ,  Ming-Tzong Yang ,  Chung-Cheng Wu

IPC: G11C17/12 ,  H01L27/112 ,  G11C11/34

CPC classification number: G11C17/12 ,  H01L27/112

Abstract: A memory cell and a process for making it are disclosed. The ROM code is not implanted in the floating gate for cells selected to be "off". This memory cell has a much lower threshold voltage than conventional cells and the implantation induced crystal damage is avoided.

Abstract translation: 公开了一种存储单元及其制造方法。 对于选择为“关闭”的单元，ROM码不会植入浮动门。 该存储单元具有比常规电池低得多的阈值电压，并且避免了注入诱导的晶体损伤。