公开(公告)号：US06777280B2

公开(公告)日：2004-08-17

申请号：US10136498

申请日：2002-04-30

申请人： Li-Chun Li ,  Huoy-Jong Wu ,  Chung-Cheng Wu ,  Saysamone Pittikoun ,  Wen-Wei Lo

发明人： Li-Chun Li ,  Huoy-Jong Wu ,  Chung-Cheng Wu ,  Saysamone Pittikoun ,  Wen-Wei Lo

IPC分类号： H01L218238

CPC分类号： H01L27/10894 ,  H01L21/761 ,  H01L21/76202 ,  H01L27/10897

摘要： Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order to block the channels stop implant from an N+ contact region used for DNW biasing. In DRAMs and other integrated circuits, a minimal spacing requirement between a well of an integrated circuit on the one hand and adjacent circuitry on the other hand is eliminated by laying out the adjacent circuitry so that the well is located adjacent to a transistor having an electrode connected to the same voltage as the voltage that biases the well. For example, in DRAMs, the minimal spacing requirement between the DNW and the read/write circuitry is eliminated by locating the DNW next to a transistor precharging the bit lines before memory accesses. One electrode of the transistor is connected to a precharge voltage. This electrode overlaps the DNW which is biased to the same precharge voltage. This electrode provides the DNW N+ contact region.

公开(公告)号：US6133597A

公开(公告)日：2000-10-17

申请号：US900560

申请日：1997-07-25

申请人： Li-Chun Li ,  Huoy-Jong Wu ,  Chung-Cheng Wu ,  Saysamone Pittikoun ,  Wen-Wei Lo

发明人： Li-Chun Li ,  Huoy-Jong Wu ,  Chung-Cheng Wu ,  Saysamone Pittikoun ,  Wen-Wei Lo

IPC分类号： H01L21/761 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10894 ,  H01L21/761 ,  H01L21/76202 ,  H01L27/10897

摘要： Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order to block the channels stop implant from an N+ contact region used for DNW biasing. In DRAMs and other integrated circuits, a minimal spacing requirement between a well of an integrated circuit on the one hand and adjacent circuitry on the other hand is eliminated by laying out the adjacent circuitry so that the well is located adjacent to a transistor having an electrode connected to the same voltage as the voltage that biases the well. For example, in DRAMs, the minimal spacing requirement between the DNW and the read/write circuitry is eliminated by locating the DNW next to a transistor precharging the bit lines before memory accesses. One electrode of the transistor is connected to a precharge voltage. This electrode overlaps the DNW which is biased to the same precharge voltage. This electrode provides the DNW N+ contact region.

摘要翻译： 动态随机存取存储器（DRAM）单元形成在偏置深N阱（DNW）中形成的P阱中。 在N个阱中形成PMOS晶体管。 NMOS通道停止注入掩模被修改为不是N阱掩模的反向，以阻止通道从用于DNW偏置的N +接触区域停止注入。 在DRAM和其他集成电路中，通过布置相邻电路来消除一方面集成电路的阱与另一方面的相邻电路之间的最小间隔要求，使得阱位于与具有电极的晶体管相邻的位置 连接到与电压偏压相同的电压。 例如，在DRAM中，通过将存储器访问之前的位线预先充电的晶体管旁边的DNW定位在DNW和读/写电路之间的最小间隔要求被消除。 晶体管的一个电极连接到预充电电压。 该电极与被偏置到相同预充电电压的DNW重叠。 该电极提供DNW N +接触区域。

公开(公告)号：US06406953B1

公开(公告)日：2002-06-18

申请号：US09053557

申请日：1998-04-01

申请人： Li-Chun Li ,  Huoy-Jong Wu ,  Chung-Cheng Wu ,  Saysamone Pittikoun ,  Wen-Wei Lo

发明人： Li-Chun Li ,  Huoy-Jong Wu ,  Chung-Cheng Wu ,  Saysamone Pittikoun ,  Wen-Wei Lo

IPC分类号： H01L218238

CPC分类号： H01L27/10894 ,  H01L21/761 ,  H01L21/76202 ,  H01L27/10897

摘要： Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order-to block the channels stop implant from an N+ contact region used for DNW biasing. In DRAMS and other integrated circuits, a minimal spacing requirement between a well of an integrated circuit on the one hand and adjacent circuitry on the other hand is eliminated by laying out the adjacent circuitry so that the well is located adjacent to a transistor having an electrode connected to the same voltage as the voltage that biases the well. For example, in DRAMs, the minimal spacing requirement between the DNW and the read/write circuitry is eliminated by locating the DNW next to a transistor precharging the bit lines before memory accesses. One electrode of the transistor is connected to a precharge voltage. This electrode overlaps the DNW which is biased to the same precharge voltage. This electrode provides the DNW N+ contact region.

摘要翻译： 动态随机存取存储器（DRAM）单元形成在偏置深N阱（DNW）中形成的P阱中。 在N个阱中形成PMOS晶体管。 NMOS通道停止注入掩模被修改为不是N阱掩模的反向，以阻止通道从用于DNW偏置的N +接触区域停止注入。 在DRAMS和其他集成电路中，通过布置相邻电路来消除一方面集成电路的阱与相邻电路之间的最小间隔要求，使得阱位于与具有电极的晶体管相邻的位置 连接到与电压偏压相同的电压。 例如，在DRAM中，通过将存储器访问之前的位线预先充电的晶体管旁边的DNW定位在DNW和读/写电路之间的最小间隔要求被消除。 晶体管的一个电极连接到预充电电压。 该电极与被偏置到相同预充电电压的DNW重叠。 该电极提供DNW N +接触区域。

公开(公告)号：US06331721B1

公开(公告)日：2001-12-18

申请号：US09264210

申请日：1999-03-05

申请人： Kuo-Tung Sung ,  Wen-Ting Chu ,  Huoy-Jong Wu

发明人： Kuo-Tung Sung ,  Wen-Ting Chu ,  Huoy-Jong Wu

IPC分类号： H01L29788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/42328

摘要： An E2PROM or a flash memory cell having a sharp tip or thin wedge at one of its gates, e.g., the floating gate, for the erasure of electrical charges stored in the floating gate. A recess is formed between a first polysilicon gate and the substrate by removing portions of an insulating layer interposed between the first gate and the substrate. Another insulating layer, e.g., thermal oxide, is formed on the exposed portions of the first gate and the substrate, and partially fills the recess. A second polysilicon layer is formed on the thermal oxide and patterned to form a floating gate. The partially filled recess causes a sharp polysilicon tip or thin wedge to be formed as part of the floating gate. This sharp tip or thin wedge can generate a high electrical field that facilitates the removal of the stored electrical charges from the floating gate.

摘要翻译： E2PROM或闪存单元在其门之一（例如浮置栅极）处具有尖锐尖端或薄楔形，用于擦除存储在浮动栅极中的电荷。 通过去除介于第一栅极和衬底之间的绝缘层的部分，在第一多晶硅栅极和衬底之间形成凹部。 在第一栅极和衬底的暴露部分上形成另一绝缘层，例如热氧化物，并且部分地填充凹部。 第二多晶硅层形成在热氧化物上并被图案化以形成浮栅。 部分填充的凹槽使得形成尖锐的多晶硅尖端或薄楔形物作为浮动栅极的一部分。 这个尖锐的尖端或薄的楔子可以产生高电场，便于从浮动栅极去除存储的电荷。

公开(公告)号：US06194269B1

公开(公告)日：2001-02-27

申请号：US09036542

申请日：1998-03-06

申请人： Kuo-Tung Sung ,  Huoy-Jong Wu

发明人： Kuo-Tung Sung ,  Huoy-Jong Wu

IPC分类号： H01L218247

CPC分类号： H01L27/11526 ,  H01L27/11541 ,  H01L27/11543 ,  H01L29/42324

摘要： Methods to improve cell performance in ROM semiconductor integrated circuit devices, in particular split gate cell flash EEPROM devices, without the need for increasing cell size or for decreasing tunnel oxide thickness. The threshold voltage under a first gate electrode (140) is adjusted using a first impurity introducing step, such as an ion implant, and the threshold voltage under a split gate electrode (170) is also adjusted using a second impurity introducing step, such as an ion implant. Depending on the type of cell used, the first gate electrode or the split gate electrode may be used as a floating gate electrode and the threshold voltage under the floating gate electrode may be adjusted separately from the other gate electrode to provide improved cell erase performance, with or without increasing the cell size or decreasing the tunnel oxide thickness.

摘要翻译： 提高ROM半导体集成电路器件，特别是分裂栅极单元快闪EEPROM器件中的电池性能的方法，而不需要增加电池尺寸或减小隧道氧化物厚度。 第一栅电极（140）下的阈值电压使用离子注入等第一杂质导入工序进行调整，分割栅电极（170）下的阈值电压也使用第二杂质导入工序 离子注入 根据所使用的单元的类型，第一栅极电极或分离栅极电极可以用作浮置栅极电极，并且浮置栅电极下方的阈值电压可以与另一个栅电极分开调整，以提供改善的电池擦除性能， 具有或不增加电池尺寸或减小隧道氧化物厚度。

公开(公告)号：US06044018A

公开(公告)日：2000-03-28

申请号：US107172

申请日：1998-06-17

申请人： Kuo-Tung Sung ,  Huoy-Jong Wu

发明人： Kuo-Tung Sung ,  Huoy-Jong Wu

IPC分类号： G11C16/04

CPC分类号： G11C16/0441 ,  G11C2216/10

摘要： A single-poly flash memory cell manufacturable by a standard CMOS fabrication process. A NMOS floating gate (32) is electrically connected to a PMOS floating gate (34). Both gates are fabricated in a single polysilicon process and form a flash memory cell. The floating gates are programmed by Vcc to the source (14) and drain (26) of the NMOS device (28), while applying about -Vcc to the source (20) of the PMOS device (30). Band-to-band hot electrons charge the floating gates. Biasing the NMOS device to operate as a FET allows the charge state of the gate to be sensed from the source current drawn. The memory cell is erased by applying a moderately high voltage to the source (14) NMOS device while negatively biasing the drain (22) of the PMOS device. In a particular embodiment, an integrated circuit device includes a CMOS circuit and a single-poly flash memory circuit. In a further embodiment, a DC-DC on-chip voltage converter produces the erase voltage from conventional CMOS voltage supplies.

摘要翻译： 可通过标准CMOS制造工艺制造的单聚焦闪存单元。 NMOS浮动栅极（32）电连接到PMOS浮置栅极（34）。 两个栅极均采用单个多晶硅工艺制造，形成闪存单元。 浮动栅极由Vcc编程到NMOS器件（28）的源极（14）和漏极（26），同时向PMOS器件（30）的源极（20）施加约-Vcc。 带对带热电子对浮动栅极充电。 对NMOS器件进行偏置作为FET进行工作，可以从绘制的源极电流检测栅极的电荷状态。 通过对源极（14）NMOS器件施加适度的高电压而对PMOS器件的漏极（22）施加负偏压来擦除存储器单元。 在特定实施例中，集成电路器件包括CMOS电路和单聚焦闪存电路。 在另一实施例中，DC-DC片上电压转换器从常规CMOS电压源产生擦除电压。

公开(公告)号：US5963806A

公开(公告)日：1999-10-05

申请号：US916758

申请日：1997-08-19

申请人： Kuo-Tung Sung ,  Wen-Ting Chu ,  Huoy-Jong Wu

发明人： Kuo-Tung Sung ,  Wen-Ting Chu ,  Huoy-Jong Wu

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423

CPC分类号： H01L29/66825 ,  H01L29/42324 ,  H01L29/42328 ,  H01L21/28273

摘要： A method of fabricating an E.sup.2 PROM or a flash memory cell having a sharp tip or thin wedge at one of its gates, e.g., the floating gate, for the erasure of electrical charges stored in the floating gate. A recess is formed between a first polysilicon gate and the substrate by removing portions of an insulating layer interposed between the first gate and the substrate. Another insulating layer, e.g., thermal oxide, is formed on the exposed portions of the first gate and the substrate, and partially fills the recess. A second polysilicon layer is formed on the thermal oxide and patterned to form a floating gate. The partially filled recess causes a sharp polysilicon tip or thin wedge to be formed as part of the floating gate. This sharp tip or thin wedge can generate a high electrical field that facilitates the removal of the stored electrical charges from the floating gate.

摘要翻译： 一种制造E2PROM或闪存单元的方法，其在其门之一（例如浮置栅极）处具有尖锐尖端或薄楔形，用于擦除存储在浮动栅极中的电荷。 通过去除介于第一栅极和衬底之间的绝缘层的部分，在第一多晶硅栅极和衬底之间形成凹部。 在第一栅极和衬底的暴露部分上形成另一绝缘层，例如热氧化物，并且部分地填充凹部。 第二多晶硅层形成在热氧化物上并被图案化以形成浮栅。 部分填充的凹槽使得形成尖锐的多晶硅尖端或薄楔形物作为浮动栅极的一部分。 这个尖锐的尖端或薄的楔子可以产生高电场，便于从浮动栅极去除存储的电荷。