公开(公告)号：US06459482B1

公开(公告)日：2002-10-01

申请号：US09729294

申请日：2000-12-04

申请人： Bhanwar Singh ,  Ramkumar Subramanian ,  Khoi A. Phan ,  Bharath Rangarajan ,  Michael K. Templeton ,  Sanjay K. Yedur ,  Bryan K. Choo

发明人： Bhanwar Singh ,  Ramkumar Subramanian ,  Khoi A. Phan ,  Bharath Rangarajan ,  Michael K. Templeton ,  Sanjay K. Yedur ,  Bryan K. Choo

IPC分类号： G01J110

CPC分类号： H01J37/28 ,  H01J2237/2826

摘要： The present invention provides SEM systems, SEM calibration standards, and SEM calibration methods that improved accuracy in critical dimension measurements. The calibration standards have features formed with an amorphous material such as amorphous silicon. Amorphous materials lack the crystal grain structure of materials such as polysilicon and are capable of providing sharper edged features and higher accuracy patterns than grained materials. The amorphous material can be bound to a silicon wafer substrate through an intermediate layer of material, such as silicon dioxide. Where the intermediate layer is insulating material, as is silicon dioxide, the intermediate layer may be patterned with gaps to provide for electrical communication between the amorphous silicon and the silicon wafer. Charges imparted to the amorphous silicon during electron beam scanning may thereby drain to the silicon wafer rather than accumulating to a level where they would distort the electron beam.

摘要翻译： 本发明提供SEM系统，SEM校准标准和SEM校准方法，提高了临界尺寸测量的精度。 校准标准品具有非晶体材料如非晶硅形成的特征。 无定形材料缺乏诸如多晶硅的材料的晶粒结构，并且能够提供比颗粒材料更尖锐的边缘特征和更高精度的图案。 非晶材料可以通过诸如二氧化硅的材料的中间层与硅晶片衬底结合。 在中间层是绝缘材料的情况下，如二氧化硅那样，中间层可以用间隙图案化以提供非晶硅和硅晶片之间的电连通。 因此，在电子束扫描期间赋予非晶硅的电荷可以从而被排出到硅晶片，而不是积聚到它们会使电子束变形的水平。

公开(公告)号：US06451621B1

公开(公告)日：2002-09-17

申请号：US10050732

申请日：2002-01-16

申请人： Bharath Rangarajan ,  Bhanwar Singh ,  Ramkumar Subramanian

发明人： Bharath Rangarajan ,  Bhanwar Singh ,  Ramkumar Subramanian

IPC分类号： H01L2166

CPC分类号： H01L22/12

摘要： The present invention provides systems and methods wherein scatterometry is used to control an implant processes, such as an angled implant process. According to the invention, data relating to resist dimensions is obtained by scatterometry prior to an the implant process. The data is used to determine whether a resist is suitable for an implant process and/or determine an appropriate condition, such as an angle of implant or implantation dose, for an implant process.

摘要翻译： 本发明提供了系统和方法，其中使用散射法来控制植入过程，例如成角度的植入过程。 根据本发明，与抗蚀剂尺寸相关的数据通过在植入工艺之前的散射测量获得。 该数据用于确定抗蚀剂是否适合于植入过程，和/或确定用于植入过程的适当条件，例如植入角度或植入剂量。

公开(公告)号：US06445072B1

公开(公告)日：2002-09-03

申请号：US09617158

申请日：2000-07-17

申请人： Ramkumar Subramanian ,  Bhanwar Singh ,  Michael K. Templeton ,  Bharath Rangarajan

发明人： Ramkumar Subramanian ,  Bhanwar Singh ,  Michael K. Templeton ,  Bharath Rangarajan

IPC分类号： H01L214763

CPC分类号： H01L21/7682 ,  Y10S977/897

摘要： One aspect of the present invention relates to a method of forming an innerlayer dielectric, involving the steps of providing a substrate having at least two metal lines thereon; providing a conformal insulation layer over the substrate and metal lines; forming a second insulation layer over the conformal insulation layer, the second insulation layer containing a void positioned between two metal lines; at least one of thinning and planarizing the second insulation layer; and forming a third insulation layer over the second insulation layer. Another aspect of the present invention relates to an innerlayer dielectric semiconductor structure, containing a semiconductor substrate having at least two metal lines thereon; a conformal insulation layer over the semiconductor substrate and metal lines, the conformal insulation layer having a substantially uniform thickness from about 250 Å to about 5,000 Å; a second insulation layer over the conformal insulation layer, the second insulation layer containing a void positioned between two metal lines; and a third insulation layer over the second insulation layer.

摘要翻译： 本发明的一个方面涉及一种形成内层电介质的方法，包括以下步骤：提供其上具有至少两条金属线的基底; 在衬底和金属线上提供保形绝缘层; 在所述保形绝缘层上形成第二绝缘层，所述第二绝缘层包含位于两条金属线之间的空隙; 将所述第二绝缘层变薄和平坦化的至少一个; 以及在所述第二绝缘层上形成第三绝缘层。 本发明的另一方面涉及一种内层电介质半导体结构，其包含其上具有至少两条金属线的半导体衬底; 半导体衬底和金属线上的共形绝缘层，保形绝缘层具有从大约至大约等于的大致均匀的厚度; 在保形绝缘层之上的第二绝缘层，所述第二绝缘层包含位于两个金属线之间的空隙; 以及在所述第二绝缘层上的第三绝缘层。

公开(公告)号：US06413857B1

公开(公告)日：2002-07-02

申请号：US09824349

申请日：2001-04-02

申请人： Ramkumar Subramanian ,  Bharath Rangarajan ,  Bhanwar Singh

发明人： Ramkumar Subramanian ,  Bharath Rangarajan ,  Bhanwar Singh

IPC分类号： H01L214763

CPC分类号： H01L29/66772 ,  H01L21/743 ,  H01L21/84 ,  H01L29/78612 ,  H01L29/78645 ,  H01L29/78648

摘要： An SOI device structure is provided which facilitates mitigation of charge build up caused by floating body effects. A plurality of local interconnects are formed from a top insulating layer to a top silicon layer of the SOI device structure. A ground contact is then formed from the top insulating layer to a bottom substrate layer of the SOI device structure. The ground contact extends through the insulating layer, an isolation region and an oxide layer to the bottom substrate layer.

摘要翻译： 提供了SOI器件结构，其有助于减轻由浮体效应引起的电荷积累。 多个局部互连由SOI器件结构的顶部绝缘层到顶部硅层形成。 然后从顶部绝缘层到SOI器件结构的底部基底层形成接地触点。 接地触头延伸穿过绝缘层，隔离区域和氧化物层延伸到底部基底层。

公开(公告)号：US06354133B1

公开(公告)日：2002-03-12

申请号：US09729293

申请日：2000-12-04

申请人： Sanjay K. Yedur ,  Bhanwar Singh ,  Bryan K. Choo ,  Michael K. Templeton ,  Ramkumar Subramanian

发明人： Sanjay K. Yedur ,  Bhanwar Singh ,  Bryan K. Choo ,  Michael K. Templeton ,  Ramkumar Subramanian

IPC分类号： G01B528

CPC分类号： G01Q40/02 ,  G01Q40/00 ,  Y10S977/742 ,  Y10S977/842 ,  Y10S977/849 ,  Y10S977/85 ,  Y10S977/876 ,  Y10S977/901

摘要： The present invention provides systems, methods, and standards for calibrating nano-measuring devices. Calibration standards of the invention include carbon nanotubes and methods of the invention involve scanning carbon nanotubes using nano-scale measuring devices. The widths of the carbon nanotube calibration standards are known with a high degree of accuracy. The invention allows calibration of a wide variety of nano-scale measuring devices, taking into account many, and in some cases all, of the systematic errors that may affect a nano-scale measurement. The invention may be used to accurately calibrate line width, line height, and trench width measurements and may be used to precisely characterize both scanning probe microscope tips and electron microscope beams.

摘要翻译： 本发明提供了用于校准纳米测量装置的系统，方法和标准。 本发明的校准标准包括碳纳米管，本发明的方法涉及使用纳米级测量装置扫描碳纳米管。 碳纳米管校准标准品的宽度以高精度已知。 考虑到可能影响纳米尺度测量的许多系统误差以及在所有这些系统误差中，本发明允许校准各种各样的纳米尺度的测量装置。 本发明可以用于精确校准线宽，线高度和沟槽宽度测量，并且可以用于精确地表征扫描探针显微镜尖端和电子显微镜束。

公开(公告)号：US06326231B1

公开(公告)日：2001-12-04

申请号：US09207562

申请日：1998-12-08

申请人： Ramkumar Subramanian ,  Bhanwar Singh ,  Sanjay K. Yedur ,  Marina V. Plat ,  Christopher F. Lyons ,  Bharath Rangarajan ,  Michael K. Templeton

发明人： Ramkumar Subramanian ,  Bhanwar Singh ,  Sanjay K. Yedur ,  Marina V. Plat ,  Christopher F. Lyons ,  Bharath Rangarajan ,  Michael K. Templeton

IPC分类号： H01L2100

CPC分类号： H01L21/32139 ,  H01L21/0276 ,  H01L21/3143 ,  H01L21/3145

摘要： In one embodiment, the present invention relates to a method of forming a silicon oxynitride antireflection coating over a metal layer, involving the steps of providing a semiconductor substrate comprising the metal layer over at least part of the semiconductor substrate; depositing a silicon oxynitride layer over the metal layer having a thickness from about 100 Å to about 150 Å; and forming an oxide layer having a thickness from about 5 Å to about 50 Å over the silicon oxynitride layer to provide the silicon oxynitride antireflection coating. In another embodiment, the present invention relates to a method of reducing an apparent reflectivity of a metal layer having a first reflectivity in a semiconductor structure, involing forming a silicon oxynitride antireflection coating over the metal layer; wherein the silicon oxynitride antireflection coating formed over the metal layer has a second reflectivity and is formed by depositing silicon oxynitride on the metal layer by chemical vapor deposition and forming an oxide layer over the oxynitride, and the difference between the first reflectivity and the second reflectivity is at least about 60%.

摘要翻译： 在一个实施方案中，本发明涉及在金属层上形成氮氧化硅抗反射涂层的方法，包括以下步骤：在半导体衬底的至少一部分上提供包括金属层的半导体衬底; 在所述金属层上沉积厚度为约至约的氧氮化硅层; 并在氮氧化硅层上形成厚度约为5-20埃的氧化物层，以提供氮氧化硅抗反射涂层。 在另一个实施方案中，本发明涉及一种在半导体结构中减少具有第一反射率的金属层的表观反射率的方法，包括在金属层上形成氮氧化硅抗反射涂层; 其中形成在所述金属层上的所述氧氮化硅抗反射涂层具有第二反射率，并且通过化学气相沉积在所述金属层上沉积氧氮化硅并在所述氧氮化物上形成氧化物层，并且所述第一反射率和所述第二反射率之间的差异 至少约60％。

公开(公告)号：US06262484B1

公开(公告)日：2001-07-17

申请号：US09295812

申请日：1999-04-20

申请人： Bharath Rangarajan ,  Ramkumar Subramanian ,  Bhanwar Singh

发明人： Bharath Rangarajan ,  Ramkumar Subramanian ,  Bhanwar Singh

IPC分类号： H01L23485

CPC分类号： H01L21/76807

摘要： A dual damascene process and structure for fabricating semiconductor devices are disclosed. In one embodiment of the invention, a protection layer is deposited on top of a metal layer to protect the metal layer during subsequent etching of an oxide layer to form the via and damascene trench. Because the selectivity between the oxide layer and the protection layer is high, the number and complexity of processing steps are thereby reduced. Other embodiments of the present invention use a metal sealant layer and/or anti-reflective coating in conjunction with the protection layer in a dual-damascene process.

公开(公告)号：US06255202B1

公开(公告)日：2001-07-03

申请号：US09619836

申请日：2000-07-20

申请人： Christopher F. Lyons ,  Ramkumar Subramanian ,  Bhanwar Singh ,  Marina Plat

发明人： Christopher F. Lyons ,  Ramkumar Subramanian ,  Bhanwar Singh ,  Marina Plat

IPC分类号： H01L213205

CPC分类号： H01L29/66583 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/76807 ,  H01L29/4238 ,  H01L29/4925

摘要： A method for fabricating a T-gate structure is provided. A structure is provided that has a silicon layer having a gate oxide layer, a polysilicon layer over the gate oxide layer and an insulating layer over the gate oxide layer. An opening is formed extending partially into the insulating layer. The opening in the insulating layer extends from a top surface of the insulating layer to a first depth. Spacers are then formed on the sides of the opening. The opening is then extended in the insulating layer from the first depth to a second depth. The opening is wider from the top surface of the insulating layer to the first depth than the opening is from the first depth to the second depth. The spacers are then removed from the opening. The opening is then filled with a conductive material to form a T-gate structure.

摘要翻译： 提供了一种制造T型栅结构的方法。 提供一种结构，其具有硅层，该硅层具有栅极氧化物层，栅极氧化物层上的多晶硅层和栅极氧化物层上的绝缘层。 形成部分地延伸到绝缘层中的开口。 绝缘层中的开口从绝缘层的顶表面延伸到第一深度。 然后在开口的两侧形成隔板。 然后将开口在绝缘层中从第一深度延伸到第二深度。 开口从绝缘层的顶表面到比第一深度从第一深度到第二深度的第一深度更宽。 然后将隔离物从开口中取出。 然后用导电材料填充开口以形成T形栅结构。

公开(公告)号：US06190062B1

公开(公告)日：2001-02-20

申请号：US09558492

申请日：2000-04-26

申请人： Ramkumar Subramanian ,  Khoi A. Phan ,  Bharath Rangarajan ,  Bhanwar Singh ,  Bryan K. Choo ,  Sanjay K. Yedur

发明人： Ramkumar Subramanian ,  Khoi A. Phan ,  Bharath Rangarajan ,  Bhanwar Singh ,  Bryan K. Choo ,  Sanjay K. Yedur

IPC分类号： G03D1300

CPC分类号： H01J37/28 ,  H01J2237/2817

摘要： One aspect of the present invention relates to a method of inspecting a patterned substrate using an SEM, involving the steps of evaluating the patterned substrate to determine if charges exist thereon; introducing the patterned substrate having charges thereon into a processing chamber of the SEM; inspecting the patterned resist using an electron beam generated by the SEM; and introducing a cleaner containing ozone into the processing chamber of the SEM. Another aspect of the present invention relates to a system for processing a patterned substrate, containing a charge sensor for determining if charges exist on the patterned substrate and measuring the charges; a means for contacting the patterned substrate with a cleaner containing ozone to reduce the charges thereon; a controller for setting at least one of time of contact between the patterned substrate and the cleaner, temperature of the cleaner, concentration of ozone in the cleaner, and pressure under which contact between the patterned substrate and the cleaner occurs; and a device for inspecting the patterned substrate with an electron beam.

摘要翻译： 本发明的一个方面涉及使用SEM检查图案化衬底的方法，包括以下步骤：评估图案化衬底以确定其中是否存在电荷; 将具有电荷的图案化衬底引入到SEM的处理室中; 使用由SEM产生的电子束检查图案化的抗蚀剂; 并将含有臭氧的清洁剂引入SEM的处理室。 本发明的另一方面涉及一种用于处理图案化衬底的系统，其包含用于确定在图案化衬底上是否存在电荷并测量电荷的电荷传感器; 用于使图案化基底与含有臭氧的清洁剂接触以降低其上的电荷的装置; 用于设置图案化基板和清洁器之间的接触时间中的至少一个的控制器，清洁器的温度，清洁器中的臭氧浓度以及图案化基板和清洁器之间的接触发生的压力; 以及用于用电子束检查图案化衬底的装置。

公开(公告)号：US07799514B1

公开(公告)日：2010-09-21

申请号：US10957367

申请日：2004-10-01

申请人： Ramkumar Subramanian ,  Bhanwar Singh ,  Gilles Amblard

发明人： Ramkumar Subramanian ,  Bhanwar Singh ,  Gilles Amblard

IPC分类号： G03F7/26

CPC分类号： G03F7/265

摘要： Disclosed are methods for eliminating and/or mitigating the formation of footing and/or T-tops in a resist pattern. A substrate with or without an antireflective coating layer may be treated with an acidic composition prior to the formation of a resist layer. The acid treatment prevents the loss of photo generated acid from the resist by either quenching and/or neutralizing the bases, and thereby reduces the formation of footing. The surface of a resist layer which has been irradiated may be treated with an acidic composition prior to post-exposure bake. The acid treatment prevents the loss of photo generated acid from the resist by either compensating for the evaporation and/or neutralization of the bases and thereby prevents the formation of T-tops.

摘要翻译： 公开了用于消除和/或减轻抗蚀剂图案中的基脚和/或T形顶部的形成的方法。 具有或不具有抗反射涂层的基底可以在形成抗蚀剂层之前用酸性组合物处理。 酸处理通过淬灭和/或中和碱来防止光阻产生的酸的损失，从而减少基底的形成。 已经照射的抗蚀剂层的表面可以在曝光前烘烤之前用酸性组合物处理。 酸处理通过补偿基底的蒸发和/或中和来防止光致抗蚀剂产生的光的损失，从而防止形成T形顶部。