公开(公告)号：US6008089A

公开(公告)日：1999-12-28

申请号：US033376

申请日：1998-03-02

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/8247 ,  H01L21/336

CPC分类号： H01L27/11553

摘要： A method of fabricating a split gate flash memory. A substrate is provided for implantation with first ions to form a source region in the substrate. Second ions are implanted into the substrate to form a drain region in the substrate, wherein the source region is connected to the drain region. A part of the substrate is defined to form a number of trenches, wherein the trenches are located between the source region and the drain region. A tunneling oxide layer is formed along the profile of the trenches and on the surface of the substrate. The trenches are subsequently filled with a first polysilicon layer, wherein the depth of the first polysilicon layer is between that of the source region and that of the drain region in the substrate. An inter-dielectric layer is formed over the surface on the substrate and the first polysilicon layer, and a second polysilicon layer is formed on the substrate. The second polysilicon layer, the inter-dielectric layer, and the first poysilicon layer are defined to complete the fabricating of the flash memory device.

摘要翻译： 一种制造分离栅闪存的方法。 提供衬底用于注入第一离子以在衬底中形成源区。 将第二离子注入到衬底中以在衬底中形成漏极区，其中源极区连接到漏极区。 衬底的一部分被限定为形成多个沟槽，其中沟槽位于源极区域和漏极区域之间。 沿着沟槽的轮廓和衬底的表面形成隧道氧化物层。 沟槽随后填充有第一多晶硅层，其中第一多晶硅层的深度在源极区域和衬底中的漏极区域的深度之间。 在基板和第一多晶硅层的表面上形成介电层，在基板上形成第二多晶硅层。 限定第二多晶硅层，介质间介质层和第一多晶硅层以完成闪速存储器件的制造。

公开(公告)号：US5994185A

公开(公告)日：1999-11-30

申请号：US24163

申请日：1998-02-17

申请人： Yau-Kae Sheu ,  Gary Hong

发明人： Yau-Kae Sheu ,  Gary Hong

IPC分类号： H01L21/336 ,  H01L29/788

CPC分类号： H01L29/66825 ,  H01L29/7885

摘要： A method of fabricating a flash memory. A heavily doped region with the opposite polarity of the drain region is formed between the channel region and the drain region. The heavily doped region is in a bar shape extending towards both the drain and the source regions along a side of the floating gate. Furthermore, the reading operation is performed in reverse by applying a zero voltage to the drain region, and a non-zero voltage to the source region.

摘要翻译： 一种制造闪速存储器的方法。 在沟道区域和漏极区域之间形成具有与漏极区域相反极性的重掺杂区域。 重掺杂区域是沿浮动栅极的一侧向漏极和源极区域延伸的棒状。 此外，通过向漏极区域施加零电压并且向源极区域施加非零电压来反向执行读取操作。

公开(公告)号：US5976935A

公开(公告)日：1999-11-02

申请号：US149587

申请日：1998-09-08

申请人： Ying-Jen Lin ,  Joe Ko ,  Gary Hong

发明人： Ying-Jen Lin ,  Joe Ko ,  Gary Hong

IPC分类号： H01L21/28 ,  H01L21/336

CPC分类号： H01L21/28273

摘要： A method is provided for fabricating an EEPROM (EEPROM (electrically erasable and programmable read-only memory) device, which can help improve the quality of the tunneling oxide layer in the EEPROM device for reliable operation of the EEPROM device. This method is characterized in that the portion of the tungsten silicide (WSi) layer that is directly laid above the tunneling oxide layer is removed, while still allowing all the other part of the tungsten silicide layer to remain unaltered. As a result, in the subsequent heat-treatment process, the degradation in the quality of the tunneling oxide layer that occurs in the prior art due to the forming of a trapping center therein can be prevented. The tunneling oxide layer is thus more assured in quality, allowing the resultant EEPROM to operate reliably with high performance.

摘要翻译： 提供了一种用于制造EEPROM（EEPROM（电可擦除和可编程只读存储器）器件）的方法，其可以帮助提高EEPROM器件中隧道氧化物层的质量，以使EEPROM器件可靠地工作，该方法的特征在于 直接放置在隧道氧化物层上方的硅化钨（WSi）层的部分被去除，同时仍允许硅化钨层的所有其它部分保持不变，结果，在随后的热处理工艺 可以防止由于在其中形成捕获中心而在现有技术中发生的隧道氧化物层的质量下降，因此隧道氧化物层的质量更加确保，使得所得到的EEPROM能够高可靠地运行 性能。

公开(公告)号：US5885868A

公开(公告)日：1999-03-23

申请号：US789202

申请日：1997-01-24

申请人： Ruei-Ling Lin ,  Ching-Hsiang Hsu ,  Gary Hong

发明人： Ruei-Ling Lin ,  Ching-Hsiang Hsu ,  Gary Hong

IPC分类号： H01L21/8247 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L29/788 ,  H01L21/336

CPC分类号： H01L29/7883 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/1203

摘要： A process for fabricating compact contactless flash memory array for semiconductor EEPROM devices having a number of memory cell units is disclosed. Field oxide layers for the flash memory array are first grown over the surface of an SOI wafer. Gate oxide layers are then grown. Floating gates are then formed by patterning the first polysilicon layer. Source/drain buried bitlines for the flash memory array are formed. A first BPSG (borophosphosilicate glass) layer is deposited and then reflown and etched back. An oxide-nitride-oxide layer is formed. A second polysilicon layer is deposited with in-situ dope. A WSi.sub.x layer then forms. Stacked gates for the flash array are formed by patterning into the formed oxide-nitride-oxide, second polysilicon and WSi.sub.x layers. The stacked gates are then covered with a second BPSG layer. Contact openings for the source/drain buried lines are formed. Metal lines leading into the contact openings are then formed for interconnecting the memory cells in the flash memory array with peripheral control circuits of the semiconductor EEPROM devices.

摘要翻译： 公开了一种用于制造具有多个存储单元单元的半导体EEPROM器件的紧凑型非接触式闪速存储器阵列的方法。 闪存阵列的场氧化物层首先在SOI晶片的表面上生长。 然后生长栅极氧化物层。 然后通过图案化第一多晶硅层形成浮栅。 形成闪存阵列的源/漏掩埋位线。 沉积第一个BPSG（硼磷硅酸盐玻璃）层，然后退回并回蚀刻。 形成氧化物 - 氮化物 - 氧化物层。 第二多晶硅层沉积有原位涂料。 然后形成一个WSix层。 用于闪存阵列的堆叠栅极通过图案化形成为形成的氧化物 - 氮化物 - 氧化物，第二多晶硅和WSix层。 堆叠的栅极然后用第二个BPSG层覆盖。 形成用于源极/漏极掩埋线的接触开口。 然后形成导入接触开口的金属线，以将闪存阵列中的存储单元与半导体EEPROM器件的外围控制电路互连。

公开(公告)号：US5882970A

公开(公告)日：1999-03-16

申请号：US552428

申请日：1995-11-03

申请人： Chih-Hung Lin ,  Hwi-Huang Chen ,  Gary Hong ,  Chen-Chiu Hsue

发明人： Chih-Hung Lin ,  Hwi-Huang Chen ,  Gary Hong ,  Chen-Chiu Hsue

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L29/66825

摘要： A flash memory cell is fabricated by forming a lightly-doped region with only an implantation procedure to avoid lateral diffusion resulting from an increased overlap between the source region and gate as well as a short channel effect, while surrounding the source region with the lightly-doped region to thereby increase the breakdown voltage between the source region and the substrate.

摘要翻译： 闪存单元是通过仅通过注入步骤形成轻掺杂区域来制造的，以避免由于源区和栅极之间的重叠增加而产生的横向扩散以及短沟道效应，同时围绕源极区域， 从而增加源极区域和衬底之间的击穿电压。

公开(公告)号：US5852313A

公开(公告)日：1998-12-22

申请号：US967940

申请日：1997-11-12

申请人： Gary Hong ,  Patrick Wang ,  Wenchi Ting

发明人： Gary Hong ,  Patrick Wang ,  Wenchi Ting

IPC分类号： H01L27/115 ,  H01L29/792

CPC分类号： H01L27/115

摘要： A flash memory cell structure comprising a semiconductor substrate having a first transistor and a second transistor formed thereon. The first transistor has a stacked gate and a first source/drain regions, wherein the stacked gate further includes a floating gate and a control gate. The control gate is formed above the floating gate. The second transistor is electrically connected in series with the first transistor. The second transistor functions as a select transistor and includes a gate and a second source/drain regions.

摘要翻译： 一种闪速存储单元结构，包括具有形成在其上的第一晶体管和第二晶体管的半导体衬底。 第一晶体管具有堆叠栅极和第一源极/漏极区域，其中堆叠栅极还包括浮置栅极和控制栅极。 控制栅极形成在浮动栅极上方。 第二晶体管与第一晶体管串联电连接。 第二晶体管用作选择晶体管，并且包括栅极和第二源极/漏极区域。

公开(公告)号：US5849625A

公开(公告)日：1998-12-15

申请号：US807885

申请日：1997-02-26

申请人： Chen-Chiu Hsue ,  Gary Hong

发明人： Chen-Chiu Hsue ,  Gary Hong

IPC分类号： H01L21/762 ,  H01L2/76

CPC分类号： H01L21/76205 ,  H01L21/76237

摘要： A process for fabricating an improved planar field oxide (FOX) structure on a silicon substrate was achieved. The process involves forming recessed areas in the silicon substrate where the field oxide is require. A thin silicon oxide is formed on the surface of the recessed areas as a nucleation layer and then a thicker silicon oxide layer is selectively deposited in the recess areas by Liquid Phase Deposition (LPD). The planar FOX structure formed by LPD can be used in conjunction with a FOX structure formed by the conventional LOCal Oxidation of Silicon (LOCOS) process on the same substrate. The planar field oxide formed by LPD eliminates the bird beak structure and the lateral diffusion of the channel stop implant commonly associated with the LOCOS structure.

摘要翻译： 实现了在硅衬底上制造改进的平面场氧化物（FOX）结构的工艺。 该方法包括在需要场氧化物的硅衬底中形成凹陷区域。 在凹陷区域的表面上形成薄的氧化硅作为成核层，然后通过液相沉积（LPD）在凹陷区域中选择性地沉积更厚的氧化硅层。 由LPD形成的平面FOX结构可以与在同一衬底上通过常规的局部氧化硅（LOCOS）工艺形成的FOX结构结合使用。 由LPD形成的平面场氧化物消除了鸟喙结构和通常与LOCOS结构相关联的通道停止植入物的横向扩散。

公开(公告)号：US5716884A

公开(公告)日：1998-02-10

申请号：US682403

申请日：1996-07-17

申请人： Chen-Chiu Hsue ,  Gary Hong ,  Ming-Tzong Yang

发明人： Chen-Chiu Hsue ,  Gary Hong ,  Ming-Tzong Yang

IPC分类号： H01L21/8242

CPC分类号： H01L27/10852

摘要： A method for fabricating a capacitor having a fin-shaped electrode on a dynamic random access memory (DRAM) cell having increased capacitance was achieved. The capacitor is fabricated on a silicon substrate having an active device region. The device region contains a metal-oxide-semiconductor field effect transistor (MOSFET), having one capacitor aligned over and contacting the source/drain of the MOSFET in the device region. The capacitor is increased in capacitance by forming a multilayer insulator structure over the storage capacitor area and recessing alternate layers, then using the form as a mold for forming a polysilicon fin-like bottom capacitor electrode. The remaining multilayer mold is removed and a high dielectric constant insulator is deposited on the bottom electrode as the inter-electrode dielectric. The top capacitor electrode is formed by depositing a doped polysilicon layer which also fills the recesses in the bottom electrode forming inter-digitized fin-shaped top and bottom capacitor electrodes and completing a dynamic random access memory (DRAM) cell.

摘要翻译： 实现了在具有增加的电容的动态随机存取存储器（DRAM）单元上制造具有鳍状电极的电容器的方法。 电容器制造在具有有源器件区域的硅衬底上。 器件区域包含一个金属氧化物半导体场效应晶体管（MOSFET），其中一个电容器对准器件区域中与MOSFET的源极/漏极对准并接触。 通过在存储电容器区域和凹陷交替层上形成多层绝缘体结构，然后使用该形式作为形成多晶硅鳍状底部电容器电极的模具，电容器增加电容。 去除剩余的多层模具，并且在底部电极上沉​​积高介电常数绝缘体作为电极间电介质。 顶部电容器电极通过沉积掺杂多晶硅层而形成，掺杂多晶硅层还填充底部电极中的凹陷，形成数字化的鳍状顶部和底部电容器电极，并完成动态随机存取存储器（DRAM）单元。

公开(公告)号：US5700708A

公开(公告)日：1997-12-23

申请号：US665386

申请日：1996-06-18

申请人： Hwi-Huang Chen ,  Gary Hong

发明人： Hwi-Huang Chen ,  Gary Hong

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A process for fabricating a storage capacitor for memory cell units of a DRAM memory device to achieve an increased capacitance value. The process includes first forming a transistor including a gate, a source region, and a drain region on the silicon substrate of the device. The gate includes a first polysilicon layer covered by an insulating layer. A silicon nitride layer is formed covering the transistor and a silicon oxide layer is formed on the silicon nitride layer. A contact opening is formed in the silicon oxide layer and the silicon nitride layer which exposes the surface of the transistor drain/source region. The silicon oxide layer has an edge portion extending toward the cavity of the contact opening more than the edge of the silicon nitride layer below it extends. A second polysilicon layer is then formed in the contact opening, covering the exposed drain region, the gate, and the edge portion of the silicon oxide layer and the silicon nitride layer. The second polysilicon layer thus provides the first electrode of the storage capacitor. A dielectric layer is formed on the second polysilicon layer to provide the dielectric of the storage capacitor and a third polysilicon layer is formed on the dielectric layer to provide the second electrode of the storage capacitor.

摘要翻译： 一种用于制造DRAM存储器件的存储单元单元的存储电容器以实现增加的电容值的过程。 该工艺包括首先在器件的硅衬底上形成包括栅极，源极区和漏极区的晶体管。 栅极包括被绝缘层覆盖的第一多晶硅层。 形成覆盖晶体管的氮化硅层，并且在氮化硅层上形成氧化硅层。 在氧化硅层和暴露晶体管漏极/源极区域的表面的氮化硅层上形成接触开口。 氧化硅层具有比其延伸的氮化硅层的边缘朝向接触开口的空腔延伸的边缘部分。 然后在接触开口中形成第二多晶硅层，覆盖暴露的漏极区域，栅极以及氧化硅层和氮化硅层的边缘部分。 因此，第二多晶硅层提供存储电容器的第一电极。 在第二多晶硅层上形成电介质层以提供存储电容器的电介质，并且在电介质层上形成第三多晶硅层以提供存储电容器的第二电极。

公开(公告)号：US5675162A

公开(公告)日：1997-10-07

申请号：US641411

申请日：1996-04-30

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A semiconductor device is formed on a substrate lightly doped with a dopant, a source region and a drain region in the substrate on the surface thereof, a dielectric layer deposited upon the substrate, a first floating gate layer formed on the dielectric layer, a second floating gate layer formed on the the first floating gate layer, a second dielectric material deposited upon the surface of the first floating gate electrode, a control gate electrode deposited upon the surface of the additional dielectric material, and means for applying a voltage to the control gate electrode.

摘要翻译： 半导体器件形成在其表面上的衬底中轻掺杂有掺杂剂，源区和漏区的衬底上，沉积在衬底上的电介质层，形成在电介质层上的第一浮栅，第二浮栅 形成在第一浮栅上的浮置栅层，沉积在第一浮栅电极的表面上的第二电介质材料，沉积在附加电介质材料的表面上的控制栅极电极，以及向控制电极施加电压的装置 栅电极。