公开(公告)号：US06268241B1

公开(公告)日：2001-07-31

申请号：US09408152

申请日：1999-09-29

申请人： Hwi-Huang Chen ,  Gary Hong

发明人： Hwi-Huang Chen ,  Gary Hong

IPC分类号： H01L218249

CPC分类号： H01L21/28052 ,  H01L29/665

摘要： A method for forming a self-aligned silicide (or called salicide) structure in IC fabrication is described. This method is characterized by the step of making the top surface of a polysilicon-based structure into a rugged surface, which allows the subsequently formed salicide structure over the rugged surface of the polysilicon-based structure to have an increased surface area and thus have a reduced sheet resistance when compared to the prior art. By this method, the first step is to prepare a semiconductor substrate, after which an oxide layer is formed over the substrate. Next, a polysilicon-based structure is formed over the oxide layer, and then the exposed surface of the polysilicon-based structure is reshaped into a rugged surface. Subsequently, a silicide layer is formed over the rugged surface of the polysilicon-based structure, which serves as the intended salicide structure.

摘要翻译： 描述了在IC制造中形成自对准硅化物（或称为自对准硅化物）结构的方法。 该方法的特征在于使基于多晶硅的结构的顶表面成为粗糙表面的步骤，其允许在多晶硅基结构的粗糙表面上随后形成的自对准硅化物结构具有增加的表面积，因此具有 与现有技术相比降低了薄层电阻。 通过该方法，第一步是制备半导体衬底，然后在衬底上形成氧化物层。 接下来，在氧化物层上形成多晶硅基结构，然后将多晶硅基结构的暴露表面重新成形为粗糙的表面。 随后，在多晶硅基结构的粗糙表面上形成硅化物层，其用作预期的自对准硅化物结构。

公开(公告)号：US5899718A

公开(公告)日：1999-05-04

申请号：US859259

申请日：1997-05-20

申请人： Hwi-Huang Chen ,  Joe Ko ,  Gary Hong

发明人： Hwi-Huang Chen ,  Joe Ko ,  Gary Hong

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L29/66825

摘要： A method for fabricating flash memory cells having a DDD structure that prevents leakage current during data erasure, that does not require a high temperature drive-in process, and that easily combines with other logic processes. The method for fabricating the flash memory cells utilizes ion implantation through contact windows to establish heavily doped source and drain regions inside previously formed deeply doped source and drain regions to construct the DDD structure.

摘要翻译： 一种用于制造具有DDD结构的闪存单元的方法，其防止在数据擦除期间的泄漏电流，其不需要高温驱动过程，并且易于与其他逻辑处理相结合。 用于制造闪存单元的方法利用离子注入通过接触窗口在先前形成的深掺杂源极和漏极区域内建立重掺杂的源极和漏极区域以构成DDD结构。

公开(公告)号：US06757198B2

公开(公告)日：2004-06-29

申请号：US10387712

申请日：2003-03-12

申请人： Chih-Jen Huang ,  Hwi-Huang Chen ,  Gary Hong

发明人： Chih-Jen Huang ,  Hwi-Huang Chen ,  Gary Hong

IPC分类号： G11C1604

CPC分类号： G11C16/12 ,  G11C16/14

摘要： A method for operating a non-volatile memory device, which is applicable to an n-channel non-volatile memory device, wherein a positive voltage is applied to the control gate, a negative voltage is applied to the drain region while the source region is floating. Furthermore, a negative voltage is applied to the substrate to program to the n-channel memory device by the channel Fowler-Nordheim tunneling effect. To erase the n-channel non-volatile memory device, a negative voltage is applied to the control gate, a positive voltage is applied to the drain region, and the source region is floating. Moreover, a positive voltage is applied to the substrate to erase the n-channel memory device using the channel Fowler-Nordheim tunneling effect.

摘要翻译： 一种用于操作非易失性存储器件的方法，其适用于n沟道非易失性存储器件，其中正电压被施加到控制栅极，负电压被施加到漏极区域，而源区域是 浮动 此外，通过信道Fowler-Nordheim隧道效应将负电压施加到衬底以对n沟道存储器件进行编程。 为了擦除n沟道非易失性存储器件，向控制栅极施加负电压，向漏极区域施加正电压，并且源极区域是浮置的。 此外，使用通道Fowler-Nordheim隧道效应将正电压施加到衬底以擦除n沟道存储器件。

公开(公告)号：US06077763A

公开(公告)日：2000-06-20

申请号：US752627

申请日：1996-11-19

申请人： Hwi-Huang Chen ,  Gary Hong

发明人： Hwi-Huang Chen ,  Gary Hong

IPC分类号： H01L21/60 ,  H01L21/8246 ,  H01L27/105 ,  H01L21/8238 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/76897 ,  H01L27/105 ,  H01L27/112

摘要： A process of fabricating self-aligned contacts for a semiconductor memory IC device. The substrate of the memory device has formed thereon gate structures of the memory cell units for the memory device. The gate structures are regularly spaced apart by first sidewall spacers formed on sidewalls of the gate structures. Source/drain regions of the memory cell units are formed in the device substrate in regions between consecutive gate structures. The process includes first forming an insulating layer over the surface of the substrate, followed by anisotropically etching back the insulating layer until a predetermined thickness over and normal to the top surface of the gate structure is obtained. A photoresist layer is formed over the surface of the insulating layer, with openings exposing contact regions for the memory cell units. Second sidewall spacers are then formed on the sidewalls of the gate structures and the source/drain regions are exposed, by etching into the insulating layer through the openings. The second sidewall spacers cover the first sidewall spacers. Contacts are then formed for the memory cell units, in direct electrical contact with the source/drain regions.

摘要翻译： 制造用于半导体存储器IC器件的自对准触点的工艺。 存储器件的衬底在其上形成用于存储器件的存储单元单元的栅极结构。 栅极结构通过形成在栅极结构的侧壁上的第一侧壁间隔规则地隔开。 存储单元单元的源极/漏极区域在连续栅极结构之间的区域中形成在器件衬底中。 该方法包括首先在衬底的表面上形成绝缘层，随后各向异性地蚀刻绝缘层，直到获得在栅极结构的顶表面上方并垂直于预定厚度。 在绝缘层的表面上形成光致抗蚀剂层，其中开口暴露存储单元单元的接触区域。 然后在栅极结构的侧壁上形成第二侧壁间隔物，并且通过通过开口蚀刻到绝缘层中而使源极/漏极区域暴露。 第二侧壁间隔物覆盖第一侧壁间隔物。 然后与存储单元单元形成与源极/漏极区域直接电接触的触点。

公开(公告)号：US6017796A

公开(公告)日：2000-01-25

申请号：US138757

申请日：1998-08-24

申请人： Hwi-Huang Chen ,  Gary Hong

发明人： Hwi-Huang Chen ,  Gary Hong

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L29/66825 ,  H01L27/11521

摘要： A semiconductor fabrication method for fabricating a flash EEPROM (electrically erasable and programmable read-only memory) device uses STI (shallow-trench isolation) technique to form the field oxide isolation layers so as to make the EEPROM device suitable for fabrication at the submicron level of integration. By this method, the first step is to prepare a semiconductor substrate. Next, a plurality of field oxide isolation layers are formed through the STI technique to define active region in the substrate. After this, at least one gate structure is formed within the active region, which includes a tunnel oxide layer, a first conductive layer serving as a floating gate, a dielectric layer, a second conductive layer serving as a control gate, and a topping layer. Subsequently, an ion-implantation process is performed to form source/drain regions beside the gate structure. A sidewall spacer is then formed on the sidewall of the gate structure. Next, a metallization layer is formed over the entire substrate and then an insulating layer is formed over the metallization layer. The insulating layer is then selectively removed in such a manner that the remaining part thereof covers the source region and the field oxide isolation layers neighboring the source region. Finally, all the part of the metallization layer that is uncovered by the remaining part of the insulating layer is entirely removed.

摘要翻译： 用于制造闪速EEPROM（电可擦除可编程只读存储器）器件的半导体制造方法使用STI（浅沟槽隔离）技术形成场氧化物隔离层，以使得EEPROM器件适合于在亚微米级制造 的整合。 通过该方法，第一步是制备半导体衬底。 接下来，通过STI技术形成多个场氧化物隔离层，以限定衬底中的有源区。 此后，在有源区域内形成至少一个栅极结构，该有源区包括隧道氧化物层，用作浮置栅极的第一导电层，介电层，用作控制栅极的第二导电层，以及顶层 。 随后，进行离子注入工艺以在栅极结构旁边形成源/漏区。 然后在栅极结构的侧壁上形成侧壁间隔物。 接下来，在整个基板上形成金属化层，然后在金属化层上形成绝缘层。 然后选择性地去除绝缘层，使得其余部分覆盖与源极区域相邻的源极区域和场氧化物隔离层。 最后，完全除去金属化层未被绝缘层的剩余部分覆盖的部分。

公开(公告)号：US5422292A

公开(公告)日：1995-06-06

申请号：US316504

申请日：1994-09-30

申请人： Gary Hong ,  Hwi-Huang Chen ,  Yau-Kae Sheu

发明人： Gary Hong ,  Hwi-Huang Chen ,  Yau-Kae Sheu

IPC分类号： H01L21/8247

CPC分类号： H01L27/11517

摘要： A new process for fabricating split-gate flash EEPROM memory cell on a semiconductor substrate is described. Source/drain regions are formed apart in the semiconductor substrate to define a channel there between. A tunnel oxide layer, a first conducting layer, and an dielectric layer are successfully formed overlying the semiconductor substrate. The dielectric layer, the first conducting layer, and the tunnel oxide layer are patterned by etching to expose portion of the channel and provide the first conducting layer forming a floating gate. Then, a first oxide layer is formed by thermal oxidation overlying the exposed surfaces of the floating gate and the channel. A second oxide layer is formed by deposition overlying the first oxide layer and the dielectric layer. A control gate layer is formed by depositing and etching a second conducting layer overlying the second oxide layer completing the split-gate flash EEPROM memory cell. The isolation between the floating gate and the control gate can be improved by using the first and second oxide layer, so that preventing the problem of leakage.

摘要翻译： 描述了在半导体衬底上制造分裂栅极快速EEPROM存储单元的新工艺。 源极/漏极区域在半导体衬底中分开形成以在其间形成沟道。 隧道氧化物层，第一导电层和电介质层成功地覆盖在半导体衬底上。 介电层，第一导电层和隧道氧化物层通过蚀刻来图案化以暴露沟道的部分，并提供形成浮栅的第一导电层。 然后，通过覆盖浮动栅极和沟道的暴露表面的热氧化形成第一氧化物层。 通过覆盖第一氧化物层和电介质层的沉积形成第二氧化物层。 通过沉积和蚀刻覆盖在完成分裂栅极快速EEPROM存储单元的第二氧化物层上的第二导电层来形成控制栅极层。 可以通过使用第一和第二氧化物层来改善浮置栅极和控制栅极之间的隔离，从而防止泄漏的问题。

公开(公告)号：US06396745B1

公开(公告)日：2002-05-28

申请号：US09783868

申请日：2001-02-15

申请人： Gary Hong ,  Hwi-Huang Chen ,  Wen-Chi Ting

发明人： Gary Hong ,  Hwi-Huang Chen ,  Wen-Chi Ting

IPC分类号： G11C700

CPC分类号： G11C16/3427 ,  G11C16/0433 ,  H01L29/42324 ,  H01L29/7883

摘要： In present invention we provide a vertical two-transistor memory cell consisted of a MOS transistor and an ETOX cell. One of the drain or source of the MOS transistor is connected to the control gate of the ETOX cell, the other is acted as the control gate of the vertical two-transistor memory cell and is connected to a control line. And the gate of the MOS transistor is acted as the select gate of the vertical two-transistor memory cell and is connected to a word line. The drain of ETOX cell is connected to a bit line, and the source of ETOX cell is grounded. The vertical two-transistor memory cell can be programmed by channel Fowler-Nordheim tunneling of electrons which is injected from the substrate through the channel and tunnel oxide into the floating gate. Such memory cell can avoid the word line disturb by controlling the word line. The memory cell can be also erased by channel Fowler-Nordheim tunneling, in which the electrons is withdrawn from the floating gate through the tunnel oxide and channel to the substrate. In addition, the vertical two-transistor memory cell can be also programmed by conventional methods such as hot electron injection and drain Fowler-Nordheim tunneling, and can be also erased by negative gate source erase or drain Fowler-Nordheim tunneling erase.

摘要翻译： 在本发明中，我们提供了由MOS晶体管和ETOX单元组成的垂直双晶体管存储单元。 MOS晶体管的漏极或源极之一连接到ETOX单元的控制栅极，另一个作为垂直双晶体管存储单元的控制栅极并连接到控制线。 并且MOS晶体管的栅极用作垂直双晶体管存储单元的选择栅极并连接到字线。 ETOX电池的漏极连接到位线，ETOX电池的源极接地。 垂直双晶体管存储单元可以通过通道Fowler-Nordheim隧道进行编程，电子从基板通过沟道注入并将隧道氧化物注入浮栅。 这样的存储单元可以通过控制字线来避免字线干扰。 还可以通过通道Fowler-Nordheim隧道擦除存储单元，其中电子通过隧道氧化物和通道从浮栅取出到衬底。 此外，垂直双晶体管存储单元也可以通过诸如热电子注入和漏极Fowler-Nordheim隧道的常规方法进行编程，并且还可以通过负栅极源擦除或漏极Fowler-Nordheim隧道擦除来擦除。

公开(公告)号：US5646056A

公开(公告)日：1997-07-08

申请号：US540776

申请日：1995-10-11

申请人： Chih-Hung Lin ,  Hwi-Huang Chen ,  Gary Hong

发明人： Chih-Hung Lin ,  Hwi-Huang Chen ,  Gary Hong

IPC分类号： H01L21/336 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L21/265

CPC分类号： H01L29/456 ,  H01L29/41775 ,  H01L29/66621 ,  H01L29/78 ,  H01L29/49

摘要： In a method for fabricating a ULSI MOSFET, an additional polysilicon layer is used to form polysilicon/metal compound metal contacts on source and drain regions and a gate so as to avoid leakage current and short channel effect problems.

摘要翻译： 在制造ULSI MOSFET的方法中，使用附加的多晶硅层在源极和漏极区域和栅极上形成多晶硅/金属复合金属触点，以避免漏电流和短沟道效应问题。

公开(公告)号：US5882970A

公开(公告)日：1999-03-16

申请号：US552428

申请日：1995-11-03

申请人： Chih-Hung Lin ,  Hwi-Huang Chen ,  Gary Hong ,  Chen-Chiu Hsue

发明人： Chih-Hung Lin ,  Hwi-Huang Chen ,  Gary Hong ,  Chen-Chiu Hsue

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L29/66825

摘要： A flash memory cell is fabricated by forming a lightly-doped region with only an implantation procedure to avoid lateral diffusion resulting from an increased overlap between the source region and gate as well as a short channel effect, while surrounding the source region with the lightly-doped region to thereby increase the breakdown voltage between the source region and the substrate.

摘要翻译： 闪存单元是通过仅通过注入步骤形成轻掺杂区域来制造的，以避免由于源区和栅极之间的重叠增加而产生的横向扩散以及短沟道效应，同时围绕源极区域， 从而增加源极区域和衬底之间的击穿电压。

公开(公告)号：US5700708A

公开(公告)日：1997-12-23

申请号：US665386

申请日：1996-06-18

申请人： Hwi-Huang Chen ,  Gary Hong

发明人： Hwi-Huang Chen ,  Gary Hong

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A process for fabricating a storage capacitor for memory cell units of a DRAM memory device to achieve an increased capacitance value. The process includes first forming a transistor including a gate, a source region, and a drain region on the silicon substrate of the device. The gate includes a first polysilicon layer covered by an insulating layer. A silicon nitride layer is formed covering the transistor and a silicon oxide layer is formed on the silicon nitride layer. A contact opening is formed in the silicon oxide layer and the silicon nitride layer which exposes the surface of the transistor drain/source region. The silicon oxide layer has an edge portion extending toward the cavity of the contact opening more than the edge of the silicon nitride layer below it extends. A second polysilicon layer is then formed in the contact opening, covering the exposed drain region, the gate, and the edge portion of the silicon oxide layer and the silicon nitride layer. The second polysilicon layer thus provides the first electrode of the storage capacitor. A dielectric layer is formed on the second polysilicon layer to provide the dielectric of the storage capacitor and a third polysilicon layer is formed on the dielectric layer to provide the second electrode of the storage capacitor.

摘要翻译： 一种用于制造DRAM存储器件的存储单元单元的存储电容器以实现增加的电容值的过程。 该工艺包括首先在器件的硅衬底上形成包括栅极，源极区和漏极区的晶体管。 栅极包括被绝缘层覆盖的第一多晶硅层。 形成覆盖晶体管的氮化硅层，并且在氮化硅层上形成氧化硅层。 在氧化硅层和暴露晶体管漏极/源极区域的表面的氮化硅层上形成接触开口。 氧化硅层具有比其延伸的氮化硅层的边缘朝向接触开口的空腔延伸的边缘部分。 然后在接触开口中形成第二多晶硅层，覆盖暴露的漏极区域，栅极以及氧化硅层和氮化硅层的边缘部分。 因此，第二多晶硅层提供存储电容器的第一电极。 在第二多晶硅层上形成电介质层以提供存储电容器的电介质，并且在电介质层上形成第三多晶硅层以提供存储电容器的第二电极。