公开(公告)号：US5976935A

公开(公告)日：1999-11-02

申请号：US149587

申请日：1998-09-08

申请人： Ying-Jen Lin ,  Joe Ko ,  Gary Hong

发明人： Ying-Jen Lin ,  Joe Ko ,  Gary Hong

IPC分类号： H01L21/28 ,  H01L21/336

CPC分类号： H01L21/28273

摘要： A method is provided for fabricating an EEPROM (EEPROM (electrically erasable and programmable read-only memory) device, which can help improve the quality of the tunneling oxide layer in the EEPROM device for reliable operation of the EEPROM device. This method is characterized in that the portion of the tungsten silicide (WSi) layer that is directly laid above the tunneling oxide layer is removed, while still allowing all the other part of the tungsten silicide layer to remain unaltered. As a result, in the subsequent heat-treatment process, the degradation in the quality of the tunneling oxide layer that occurs in the prior art due to the forming of a trapping center therein can be prevented. The tunneling oxide layer is thus more assured in quality, allowing the resultant EEPROM to operate reliably with high performance.

摘要翻译： 提供了一种用于制造EEPROM（EEPROM（电可擦除和可编程只读存储器）器件）的方法，其可以帮助提高EEPROM器件中隧道氧化物层的质量，以使EEPROM器件可靠地工作，该方法的特征在于 直接放置在隧道氧化物层上方的硅化钨（WSi）层的部分被去除，同时仍允许硅化钨层的所有其它部分保持不变，结果，在随后的热处理工艺 可以防止由于在其中形成捕获中心而在现有技术中发生的隧道氧化物层的质量下降，因此隧道氧化物层的质量更加确保，使得所得到的EEPROM能够高可靠地运行 性能。

公开(公告)号：US06350677B1

公开(公告)日：2002-02-26

申请号：US09630869

申请日：2000-08-02

申请人： Joe Ko ,  Gary Hong

发明人： Joe Ko ,  Gary Hong

IPC分类号： H01L214763

CPC分类号： H01L29/6659 ,  H01L21/28518 ,  H01L29/665

摘要： A method of forming a self-aligned silicide layer. A planarization process is performed to form a gate with a planar top surface. Due to the planar top surface of the gate, the reactivity and the uniformity of thickness of the subsequently formed silicide layer on the top surface of the gate are improved, such that the resistance of the silicide is reduced, and the performance of the device is improved.

摘要翻译： 一种形成自对准硅化物层的方法。 进行平面化处理以形成具有平坦顶表面的栅极。 由于栅极的平面顶表面，栅极顶表面上随后形成的硅化物层的反应性和厚度的均匀性得到改善，使得硅化物的电阻降低，并且器件的性能为 改进。

公开(公告)号：US06180471B2

公开(公告)日：2001-01-30

申请号：US09183062

申请日：1998-10-30

申请人： Peter Chang ,  Gary Hong ,  Joe Ko

发明人： Peter Chang ,  Gary Hong ,  Joe Ko

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L29/7836

摘要： A method of fabricating a high voltage semiconductor device. A semiconductor substrate doped with a first type dopant and comprising a gate is provided. A cap oxide layer is formed on the gate optionally. A first ion implantation with a light second type dopant at a wide angle is performed to form a lightly doped region. A spacer is formed on a side wall of the gate. A second ion implantation with a heavy second type dopant is performed, so that a heavily doped region is formed within the lightly doped region.

摘要翻译： 一种制造高电压半导体器件的方法。 提供掺杂有第一类型掺杂剂并且包括栅极的半导体衬底。 可选地，在栅极上形成帽氧化物层。 进行具有广角的第二种光掺杂剂的第一离子注入以形成轻掺杂区域。 隔板形成在门的侧壁上。 执行具有重的第二类型掺杂剂的第二离子注入，使得在轻掺杂区域内形成重掺杂区域。

公开(公告)号：US5899718A

公开(公告)日：1999-05-04

申请号：US859259

申请日：1997-05-20

申请人： Hwi-Huang Chen ,  Joe Ko ,  Gary Hong

发明人： Hwi-Huang Chen ,  Joe Ko ,  Gary Hong

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L29/66825

摘要： A method for fabricating flash memory cells having a DDD structure that prevents leakage current during data erasure, that does not require a high temperature drive-in process, and that easily combines with other logic processes. The method for fabricating the flash memory cells utilizes ion implantation through contact windows to establish heavily doped source and drain regions inside previously formed deeply doped source and drain regions to construct the DDD structure.

摘要翻译： 一种用于制造具有DDD结构的闪存单元的方法，其防止在数据擦除期间的泄漏电流，其不需要高温驱动过程，并且易于与其他逻辑处理相结合。 用于制造闪存单元的方法利用离子注入通过接触窗口在先前形成的深掺杂源极和漏极区域内建立重掺杂的源极和漏极区域以构成DDD结构。

公开(公告)号：US5716874A

公开(公告)日：1998-02-10

申请号：US603248

申请日：1996-02-20

申请人： Joe Ko ,  Gary Hong ,  Chih-Hung Lin

发明人： Joe Ko ,  Gary Hong ,  Chih-Hung Lin

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L29/66825

摘要： A method of fabricating an EPROM memory increases a coupling ratio and reduces lateral diffusion by forming a gate oxide layer and a coupling insulator individually. A substrate is provided with a field oxide layer to isolate a predetermined active area. A gate oxide layer is formed on the substrate. On the field oxide layer and the gate oxide layer, a polysilicon layer is deposited and defined, whereby a portion of this polysilicon layer and gate oxide layer form a gate electrode. Using the gate electrode as a mask, the substrate is implanted with impurities to provide source and drain electrodes. A dielectric layer is formed on polysilicon layer. A contact window (via) is formed in a predetermined area of dielectric layer. An insulator is deposited and defined by etching, on dielectric layer and the contact window. On the insulator and dielectric layer, a metal contact layer is deposited and defined to cover the insulator.

摘要翻译： 制造EPROM存储器的方法通过单独形成栅极氧化物层和耦合绝缘体来增加耦合比并减小横向扩散。 衬底设置有场氧化物层以隔离预定的有效面积。 在衬底上形成栅氧化层。 在场氧化物层和栅极氧化物层上沉积并限定多晶硅层，由此该多晶硅层和栅极氧化物层的一部分形成栅电极。 使用栅电极作为掩模，衬底被注入杂质以提供源极和漏极。 介电层形成在多晶硅层上。 在电介质层的预定区域中形成接触窗（通孔）。 通过在电介质层和接触窗上进行蚀刻来沉积并限定绝缘体。 在绝缘体和电介质层上，沉积和限定金属接触层以覆盖绝缘体。

公开(公告)号：US5350710A

公开(公告)日：1994-09-27

申请号：US080536

申请日：1993-06-24

申请人： Gary Hong ,  Joe Ko

发明人： Gary Hong ,  Joe Ko

IPC分类号： H01L23/485 ,  H01L23/525 ,  H01L27/02 ,  H01L21/14

CPC分类号： H01L24/05 ,  H01L23/5252 ,  H01L27/0251 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3011

摘要： A multi-level conductive interconnection for an integrated circuit with an antifuse device is formed, in and on a silicon substrate, wherein there are large contact pad areas at the periphery of the interconnection. The antifuse device is formed from a thin dielectric between a first and second conductor and is connected to the integrated circuit, and is also connected to a ground reference through a silicon junction in the substrate. The large contact pad area is formed with a layer of metal, and is connected to the integrated circuit through the antifuse device, wherein the antifuse device electrically isolates the contact pad and the integrated circuit to prevent charge build-up during subsequent processing. There is further processing in a plasma environment that would normally produce electrical charge build-up at the gate oxide of the integrated circuit, but wherein the antifuse device prevents charge build-up. A voltage is applied to the antifuse device to create a low impedance element, and formation of the integrated circuit is completed.

摘要翻译： 在硅衬底中和硅衬底上形成用于具有反熔丝装置的集成电路的多级导电互连，其中在互连的周边处存在大的接触焊盘区域。 反熔丝装置由第一和第二导体之间的薄电介质形成，并连接到集成电路，并且还通过衬底中的硅结连接到接地基准。 大接触焊盘区域形成有一层金属，并通过反熔丝装置连接到集成电路，其中反熔丝装置电气隔离接触焊盘和集成电路，以防止后续处理期间的电荷积聚。 在等离子体环境中进一步处理通常会在集成电路的栅极氧化层产生电荷积累，但是其中反熔丝装置防止电荷积聚。 向反熔丝装置施加电压以产生低阻抗元件，并且完成集成电路的形成。

公开(公告)号：US06207535B1

公开(公告)日：2001-03-27

申请号：US09531903

申请日：2000-03-20

申请人： Kan-Yuan Lee ,  Joe Ko ,  Yang-Hui Fang ,  Gary Hong

发明人： Kan-Yuan Lee ,  Joe Ko ,  Yang-Hui Fang ,  Gary Hong

IPC分类号： H01L2176

CPC分类号： H01L21/76224 ,  Y10S148/05

摘要： A method of fabricating shallow trench isolations (STI) which forms a substrate with a patterned first oxide layer and a patterned silicon nitride layer thereon, so that active regions are defined with openings formed between the active regions. The openings are then over etched to form trenches for fabricating the STI, followed by forming a second oxide layer that conforms to a profile of the trenches. A third oxide layer is globally formed over the second oxide layer, sidewalls of the first oxide layer, and the silicon nitride layer. A thermal process is performed to densify a portion of the third oxide layer, so that a top portion of the third oxide layer is harder than a lower portion of the third oxide layer. The excessive portion of the third oxide layer above the silicon nitride layer is removed by performing chemical mechanical polishing, which planarizes a top surface of the third oxide layer in order to complete the manufacture of the STI.

摘要翻译： 制造浅沟槽隔离（STI）的方法，其形成具有图案化的第一氧化物层和其上的图案化氮化硅层的衬底，使得有源区域被限定为在有源区域之间形成的开口。 然后将这些开口过蚀刻以形成用于制造STI的沟槽，随后形成符合沟槽轮廓的第二氧化物层。 在第二氧化物层，第一氧化物层的侧壁和氮化硅层上全局形成第三氧化物层。 执行热处理以使第三氧化物层的一部分致密化，使得第三氧化物层的顶部比第三氧化物层的下部更硬。 通过进行化学机械抛光来去除氮化硅层上方的第三氧化物层的过剩部分，其平坦化第三氧化物层的顶表面以完成STI的制造。

公开(公告)号：US6159803A

公开(公告)日：2000-12-12

申请号：US186404

申请日：1998-11-04

申请人： Gary Hong ,  Joe Ko

发明人： Gary Hong ,  Joe Ko

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L29/66825

摘要： A method of fabicrating a flash memory. A semiconductor substrate having a field oxide layer which comprises a plurality of parallel oxide lines, a plurality of parallel word lines perpendicular to the parallel oxide lines, a dielectric layer having a same structure as and under the word lines, a plurality of floating gates separated by the field oxide layer from each other under the dielectric layer, and a plurality of regions encompassed by the field oxide laver and the word lines is provided. A first step of ion implantation to the substrate is performed by using the word lines as masks, so that a plurality of source regions and a plurality of drain regions are formed beside the word lines. Whereas each of the source regions and each of the drain regions are formed in the regions encompassed by the field oxide layer and the word lines. A photo-resist layer is formed to cover the drain regions. A second step of ion implantation to the substrate is performed by using the photo-resist layer and the parallel word lines as masks. The photo-resist layer is removed.

摘要翻译： 闪存的方法。 一种具有场氧化物层的半导体衬底，其包括多个平行氧化物线，垂直于所述平行氧化物线的多条平行字线，与所述字线具有相同结构的电介质层，分隔开的多个浮动栅极 通过电介质层下的场氧化物层，并且提供由场氧化物紫菜和字线包围的多个区域。 通过使用字线作为掩模来进行离子注入到衬底的第一步骤，使得在字线旁边形成多个源极区域和多个漏极区域。 而源极区域和漏极区域中的每一个形成在由场氧化物层和字线包围的区域中。 形成覆盖漏区的光刻胶层。 通过使用光致抗蚀剂层和平行字线作为掩模来进行离子注入到衬底的第二步骤。 除去光致抗蚀剂层。

公开(公告)号：US06225219B1

公开(公告)日：2001-05-01

申请号：US09467260

申请日：1999-12-20

申请人： Kan-Yuan Lee ,  Weiching Horng ,  Joe Ko ,  Gary Hong

发明人： Kan-Yuan Lee ,  Weiching Horng ,  Joe Ko ,  Gary Hong

IPC分类号： H01L2144

CPC分类号： H01L21/3105 ,  G03F7/091 ,  H01L21/0276 ,  H01L21/32139 ,  Y10S438/952

摘要： A method of stabilizing an anti-reflection coating (ARC) layer is disclosed. The method provides a substrate with a dielectric layer, a conductive layer, and the ARC layer formed thereon. The ARC layer is treated in an alloy treatment step prior to forming a photoresist layer over the ARC layer, so that the specificity of the ARC layer is stabilized to allow accurate transfer of a desired pattern. A photomask with the desired pattern is provided, while a photolithographic process is then performed to transfer the pattern onto the wafer.

摘要翻译： 公开了一种稳定抗反射涂层（ARC）层的方法。 该方法提供了具有介电层，导电层和形成在其上的ARC层的衬底。 在ARC层之前形成光致抗蚀剂层之前，在合金处理步骤中处理ARC层，使得ARC层的特异性被稳定以允许精确转移所需图案。 提供具有期望图案的光掩模，然后执行光刻工艺以将图案转印到晶片上。

公开(公告)号：US06221761B1

公开(公告)日：2001-04-24

申请号：US09467284

申请日：1999-12-20

申请人： Kan-Yuan Lee ,  Weiching Horng ,  Joe Ko ,  Gary Hong

发明人： Kan-Yuan Lee ,  Weiching Horng ,  Joe Ko ,  Gary Hong

IPC分类号： H01L214763

CPC分类号： H01L21/0276 ,  H01L21/0332 ,  H01L21/3144

摘要： A method of stabilizing an anti-reflection coating (ARC) layer is disclosed. The method provides a substrate with a dielectric layer, a conductive layer, and the ARC layer formed thereon. The ARC layer is treated in an ultraviolet (UV) curing step prior to forming a photoresist layer over the ARC layer, so that the specificity of the ARC layer is stabilized to allow an accurate pattern is replicated in the photoresist layer. A photomask with the desired pattern is provided, while a photolithographic process is then performed to transfer the pattern onto the wafer.

摘要翻译： 公开了一种稳定抗反射涂层（ARC）层的方法。 该方法提供了具有介电层，导电层和形成在其上的ARC层的衬底。 在ARC层之前形成光致抗蚀剂层之前，在紫外（UV）固化步骤中处理ARC层，使得ARC层的特异性被稳定以允许在光致抗蚀剂层中复制精确的图案。 提供具有期望图案的光掩模，然后执行光刻工艺以将图案转印到晶片上。