Method for making semiconductor device having field limiting ring
    51.
    发明授权
    Method for making semiconductor device having field limiting ring 失效
    制造具有场限制环的半导体器件的方法

    公开(公告)号:US5672528A

    公开(公告)日:1997-09-30

    申请号:US635509

    申请日:1996-04-22

    摘要: A semiconductor device characterized by a field limiting ring formed by a number of field limiting cells that define wells which are laterally diffused to form a continuous equipotential ring between interior and exterior regions of a semiconductor device. A number of active cells are formed in the interior region, and are therefore delineated from the exterior region of the device. Each of these active cells is a transistor, and preferably a field-effect transistor, whose structure is essentially identical to the field limiting cells, except that their wells are not merged but instead are isolated from each other. The field limiting ring increases the breakdown voltage and the ruggedness of device, and therefore enables the device to sustain high voltages when the device is in the off-state. The process does not require masking, implanting and diffusion steps for the sole purpose of forming the field limiting ring, but is instead fully integrated with the semiconductor process for forming the active cells. The field limiting cells also contribute to forward current conduction when the device is in the on-state, thereby lowering the on-resistance of the device.

    摘要翻译: 一种半导体器件,其特征在于由许多场限制电池形成的场限制环,所述场限制电池限定了横向扩散以在半导体器件的内部和外部区域之间形成连续等电位环的阱。 在内部区域中形成多个活性细胞,因此从装置的外部区域划出。 这些有源电池中的每一个都是晶体管,优选场效应晶体管,其结构基本上与场限制电池相同,不同之处在于它们的阱不被合并,而是相互隔离。 场限制环增加了击穿电压和器件的坚固性,因此当器件处于关断状态时,器件能够维持高电压。 该方法不需要用于形成场限制环的唯一目的的掩蔽,植入和扩散步骤,而是与用于形成活性细胞的半导体工艺完全整合。 当器件处于导通状态时,场限制单元还有助于正向电流传导,从而降低器件的导通电阻。

    Trench-gate MOSFET device and method for making the same
    52.
    发明授权
    Trench-gate MOSFET device and method for making the same 有权
    沟槽栅MOSFET器件及其制造方法

    公开(公告)号:US08735973B2

    公开(公告)日:2014-05-27

    申请号:US13462397

    申请日:2012-05-02

    IPC分类号: H01L29/78

    摘要: The embodiments of the present disclosure disclose a trench-gate MOSFET device and the method for making the trench-gate MOSFET device. The trench-gate MOSFET device comprises a curving dopant profile formed between the body region and the epitaxial layer so that the portion of the body region under the source metal contact has a smaller vertical thickness than the other portion of the body region. The trench-gate MOSFET device in accordance with the embodiments of the present disclosure has improved UIS capability compared with the traditional trench-gate MOSFET device.

    摘要翻译: 本公开的实施例公开了沟槽栅极MOSFET器件和制造沟槽栅极MOSFET器件的方法。 沟槽栅极MOSFET器件包括在体区和外延层之间形成的弯曲掺杂剂分布,使得源极金属接触下方的主体区域的部分的垂直厚度小于身体区域的另一部分。 根据本公开实施例的沟槽栅MOSFET MOSFET器件与传统沟槽栅极MOSFET器件相比具有改进的UIS能力。

    Method of fabricating a high-voltage transistor with an extended drain structure
    53.
    发明申请
    Method of fabricating a high-voltage transistor with an extended drain structure 审中-公开
    制造具有延长漏极结构的高压晶体管的方法

    公开(公告)号:US20120015491A1

    公开(公告)日:2012-01-19

    申请号:US13136843

    申请日:2011-08-12

    申请人: Donald Ray Disney

    发明人: Donald Ray Disney

    IPC分类号: H01L21/336

    摘要: A method for fabricating a high-voltage transistor with an extended drain region includes forming in a semiconductor substrate of a first conductivity type, first and second trenches that define a mesa having respective first and second sidewalls; then partially filling each of the trenches with a dielectric material that covers the first and second sidewalls. The remaining portions of the trenches are then filled with a conductive material to form first and second field plates. Source and body regions are formed in an upper portion of the mesa, with the body region separating the source from a lower portion of the mesa. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).

    摘要翻译: 一种用于制造具有延伸漏极区的高电压晶体管的方法包括在第一导电类型的半导体衬底中形成限定具有相应的第一和第二侧壁的台面的第一和第二沟槽; 然后用覆盖第一和第二侧壁的电介质材料部分地填充每个沟槽。 然后用导电材料填充沟槽的剩余部分以形成第一和第二场板。 源区和体区形成在台面的上部,体区将源与台面的下部分开。 要强调的是,该摘要被提供以符合要求抽象的规则,允许搜索者或其他读者快速确定技术公开的主题。 提交它的理解是,它不会用于解释或限制权利要求的范围或含义。 37 CFR 1.72(b)。

    High-voltage vertical transistor with edge termination structure
    54.
    发明申请
    High-voltage vertical transistor with edge termination structure 有权
    具有边缘端接结构的高压立式晶体管

    公开(公告)号:US20110018058A1

    公开(公告)日:2011-01-27

    申请号:US12807016

    申请日:2010-08-26

    申请人: Donald Ray Disney

    发明人: Donald Ray Disney

    IPC分类号: H01L29/78

    摘要: A high-voltage transistor includes a drain, a source, and one or more drift regions extending from the drain toward the source. A field plate member laterally surrounds the drift regions and is insulated from the drift regions by a dielectric layer. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).

    摘要翻译: 高压晶体管包括漏极,源极和从漏极延伸到源极的一个或多个漂移区域。 场板构件横向地围绕漂移区域并且通过介电层与漂移区域绝缘。 要强调的是,该摘要被提供以符合要求抽象的规则,允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是,它不会用于解释或限制权利要求的范围或含义。 37 CFR 1.72(b)。

    High-voltage vertical transistor with a multi-gradient drain doping profile
    56.
    发明申请
    High-voltage vertical transistor with a multi-gradient drain doping profile 失效
    具有多梯度漏极掺杂特性的高压垂直晶体管

    公开(公告)号:US20090061585A1

    公开(公告)日:2009-03-05

    申请号:US12288883

    申请日:2008-10-24

    IPC分类号: H01L21/336

    摘要: A high-voltage transistor includes first and second trenches that define a mesa in a semiconductor substrate. First and second field plate members are respectively disposed in the first and second trenches, with each of the first and second field plate members being separated from the mesa by a dielectric layer. The mesa includes a plurality of sections, each section having a substantially constant doping concentration gradient, the gradient of one section being at least 10% greater than the gradient of another section. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

    摘要翻译: 高压晶体管包括在半导体衬底中限定台面的第一和第二沟槽。 第一和第二场板构件分别设置在第一和第二沟槽中,第一和第二场板构件中的每一个通过介电层与台面分离。 台面包括多个部分,每个部分具有基本上恒定的掺杂浓度梯度,一个部分的梯度比另一部分的梯度大至少10%。 要强调的是,该摘要被提供以符合要求抽象的规则,允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是,它不会用于解释或限制权利要求的范围或含义。

    Method of fabricating a high-voltage transistor with a multi-layered extended drain structure
    59.
    发明授权
    Method of fabricating a high-voltage transistor with a multi-layered extended drain structure 有权
    制造具有多层延伸漏极结构的高压晶体管的方法

    公开(公告)号:US06667213B2

    公开(公告)日:2003-12-23

    申请号:US10278432

    申请日:2002-10-22

    申请人: Donald Ray Disney

    发明人: Donald Ray Disney

    IPC分类号: H01L21336

    摘要: A method for fabricating a high-voltage transistor with an extended drain region includes forming parallel arranged drift regions, each of which is interleaved with an insulating layer and a conducting layer that functions as a field plate. Source and body regions of opposite conductivity types are formed, with the body regions separating the source regions from the drift regions. An insulated gate is formed adjacent the body region. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure, It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).

    摘要翻译: 用于制造具有延伸漏极区域的高压晶体管的方法包括形成平行布置的漂移区域,每个漂移区域与绝缘层交互,并且导电层用作场板。 形成相反导电类型的源极和体区,其中主体区域将源极区域与漂移区域分开。 在身体区域附近形成绝缘栅极。 要强调的是,提供这个摘要是为了符合要求抽象的规则,允许搜索者或其他读者快速确定技术公开内容的主题。提交该提要的理解是,它不会被用于解释或 限制权利要求的范围或意义。 37 CFR 1.72(b)。