公开(公告)号：US20080209166A1

公开(公告)日：2008-08-28

申请号：US12121564

申请日：2008-05-15

申请人： Mayan Moudgill

发明人： Mayan Moudgill

IPC分类号： G06F15/76 ,  G06F9/02

CPC分类号： G06F9/3012 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3885 ,  G06F9/3891

摘要： A microprocessor for processing instructions comprises multiple clusters for receiving the instructions, each of the clusters having a plurality of functional units for executing the instructions, multiple register sub-files each having multiple registers for storing data for executing the instructions, wherein each of the clusters is associated with corresponding one of the register sub-files so that an instruction dispatched to a cluster is executed by accessing registers in a register sub-file associated with the cluster to which the instruction is dispatched, a register-renaming unit for renaming target registers in an instruction with registers in a register sub-file associated with a cluster to which the instruction is dispatched, and issue-queue units each of which is associated with a corresponding one of the clusters, wherein an issue-queue unit holds instruction renamed by the register-renaming unit until the renamed instruction is issued to be executed in a cluster associated with the issue-queue unit.

摘要翻译： 用于处理指令的微处理器包括用于接收指令的多个簇，每个簇具有用于执行指令的多个功能单元，每个具有多个寄存器的多个寄存器子文件用于存储用于执行指令的数据，其中每个簇 与对应的一个寄存器子文件相关联，从而通过访问与分发指令的集群相关联的寄存器子文件中的寄存器来执行发送到集群的指令，用于重命名目标寄存器的寄存器重命名单元 在与分配了指令的集群相关联的寄存器子文件中的寄存器的指令和每个与对应的一个集群相关联的发布队列单元中，其中发布队列单元保存由 注册重命名单元，直到发出重命名的指令才能在集群关联中执行 d与问题队列单位。

公开(公告)号：US07120780B2

公开(公告)日：2006-10-10

申请号：US10087880

申请日：2002-03-04

申请人： Mayan Moudgill

发明人： Mayan Moudgill

IPC分类号： G06F9/38 ,  G06F15/00

CPC分类号： G06F9/3012 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3885 ,  G06F9/3891

摘要： A microprocessor for processing instructions comprises multiple clusters for receiving the instructions, each of the clusters having a plurality of functional units for executing the instructions, multiple register sub-files each having multiple registers for storing data for executing the instructions, wherein each of the clusters is associated with corresponding one of the register sub-files so that an instruction dispatched to a cluster is executed by accessing registers in a register sub-file associated with the cluster to which the instruction is dispatched, a register-renaming unit for renaming target registers in an instruction with registers in a register sub-file associated with a cluster to which the instruction is dispatched, and issue-queue units each of which is associated with a corresponding one of the clusters, wherein an issue-queue unit holds instruction renamed by the register-renaming unit until the renamed instruction is issued to be executed in a cluster associated with the issue-queue unit.

公开(公告)号：US20110153701A1

公开(公告)日：2011-06-23

申请号：US12991877

申请日：2009-05-07

申请人： Mayan Moudgill

发明人： Mayan Moudgill

IPC分类号： G06F7/52 ,  G06F5/01

CPC分类号： G06F7/724 ,  G06F7/722 ,  G06F9/3001

摘要： A method for a Galois Field multiply includes executing first and second instructions. The first instruction includes receiving a first input, such as a first variable, receiving a second input, such as a second variable, performing a polynomial multiplication over GF(2m), using the first and second inputs, and producing a product. The second instruction includes receiving a third input, which may be the product from the first instruction, receiving a fourth input, which is a predetermined generator polynomial to operate upon the product, receiving a fifth input, which is a length of the predetermined generator polynomial, to limit operation of the predetermined generator polynomial upon the product, and computing, via the predetermined generator polynomial limited by the length, a modulus of the product with respect to a divisor. A hardware block is also described.

摘要翻译： Galois域乘法的方法包括执行第一和第二指令。 第一指令包括使用第一和第二输入接收诸如第一变量的第一输入，接收诸如第二变量的第二输入，使用GF（2m）执行多项式乘法，并产生乘积。 第二指令包括接收第三输入，其可以是来自第一指令的乘积，接收作为对产品进行操作的预定生成多项式的第四输入，接收作为预定生成多项式的长度的第五输入 ，以限制产品上的预定生成多项式的运算，并且经由长度限制的预定生成多项式计算乘积相对于除数的模数。 还描述了硬件块。

公开(公告)号：US20100115527A1

公开(公告)日：2010-05-06

申请号：US12513838

申请日：2007-11-08

申请人： Vladimir Kotlyar ,  Mayan Moudgill ,  Yurly M. Pogudin

发明人： Vladimir Kotlyar ,  Mayan Moudgill ,  Yurly M. Pogudin

IPC分类号： G06F9/38 ,  G06F9/50

CPC分类号： G06F9/5066 ,  G06F9/3826 ,  G06F9/3885 ,  G06F9/5027

摘要： A method of parallelizing a pipeline includes stages operable on a sequence of work items. The method includes allocating an amount of work for each work item, assigning at least one stage to each work item, partitioning the at least one stage into at least one team, partitioning the at least one team into at least one gang, and assigning the at least one team and the at least one gang to at least one processor. Processors, gangs, and teams are juxtaposed near one another to minimize communication losses.

摘要翻译： 流水线并行化的方法包括可在一系列工作项上操作的阶段。 该方法包括为每个工作项分配一定量的工作，为每个工作项分配至少一个阶段，将至少一个阶段划分成至少一个团队，将至少一个团队划分成至少一个团队，以及分配 至少一个团队和至少一个团伙到至少一个处理器。 处理器，帮派和团队彼此并列，以最大限度减少通信损失。

公开(公告)号：US07171438B2

公开(公告)日：2007-01-30

申请号：US10382578

申请日：2003-03-07

申请人： Mayan Moudgill ,  Vladimir Kotlyar

发明人： Mayan Moudgill ,  Vladimir Kotlyar

IPC分类号： G06F7/38

CPC分类号： G06F8/4441 ,  G06F7/49921 ,  G06F7/505

摘要： A method of formulating and solving equations that facilitate recognition of full word saturating addition and subtraction The method includes formulating, for each basis addition statement z=x+y or subtraction statement z=x−y, data flow equations that describe properties of the program statements being analyzed; and solving the data flow equations. The properties may include: (a) the values BITS of program variables as Boolean functions of the sign bits of x, y and z; (b) the condition COND under which program statements are executed as Boolean functions of the sign bits of x, y and z; and (c) the condition REACH of which values of variables reach any given use of z when overflow/underflow/neither occurs.

摘要翻译： 一种制定和求解有助于识别全字饱和加法和减法的方程的方法该方法包括为每个基础加法语句z = x + y或减法语句z = xy制定数据流方程，描述程序语句的属性 分析; 并解决数据流方程。 属性可以包括：（a）程序变量的值BITS作为x，y和z的符号位的布尔函数; （b）作为x，y和z的符号位的布尔函数执行程序语句的条件COND; 和（c）当溢出/下溢/不发生时，变量的值达到任何给定使用z的条件REACH。

公开(公告)号：US06956910B2

公开(公告)日：2005-10-18

申请号：US10299900

申请日：2002-11-20

申请人： Jin Lu ,  Mayan Moudgill

发明人： Jin Lu ,  Mayan Moudgill

IPC分类号： H04B1/707 ,  H04L25/03 ,  H04L27/20

CPC分类号： H04L27/2092 ,  H04B1/707 ,  H04B2201/70707 ,  H04L25/03834 ,  H04L27/206 ,  H04L27/2071

摘要： A method of increasing the speed of a transmitter by storing in look-up tables, modulation, spread, over-sampled and filtered samples of modulated data bits having an I and Q. The bits I and Q are differentially modulated, and the tables are indexed based on the differential modulation.

摘要翻译： 通过存储具有I和Q的调制数据位的查找表，调制，扩展，过采样和滤波样本来增加发射机的速度的方法。比特I和Q被差分调制，并且表是 基于差分调制索引。

公开(公告)号：US5758051A

公开(公告)日：1998-05-26

申请号：US747001

申请日：1996-11-05

申请人： Jaime Humberto Moreno ,  Mayan Moudgill

发明人： Jaime Humberto Moreno ,  Mayan Moudgill

IPC分类号： G06F9/38 ,  G06F11/34

CPC分类号： G06F9/3834 ,  G06F9/3863

摘要： A computer processing system stores sequences of instructions in a memory for execution by a processor unit. An out-of-order load instruction may be created, either statically or dynamically, by moving a load instruction from its original position in a sequence of instructions to an earlier position in said sequence of instructions. Such out-of-order load instruction identifies a location in memory from which to read a datum and a first destination register in which to place the datum. The present invention is a method and corresponding apparatus that utilizes data comparison to detect coherence among memory and the datum read by an out-of-order load operation. More specifically, the method consists of an interference test which controls the processor unit to read a datum from the same location in memory identified by the out-of-order load instruction and compare the newly read datum with the datum saved in the first destination register. If the values do not match, the newly read datum is placed in a second destination register and a recovery sequence is executed. The second destination register may be identical to the first destination register. The invention is applicable to static and dynamic reordering of instructions, and can be implemented using instructions or using hardware resources.

摘要翻译： 计算机处理系统将指令序列存储在存储器中以供处理器单元执行。 可以通过将指令序列中的原始位置的加载指令移动到所述指令序列中的较早位置，来静态或动态地创建无序加载指令。 这种无序加载指令识别从其读取数据的存储器中的位置和放置数据的第一目的地寄存器。 本发明是利用数据比较来检测存储器与通过无序加载操作读取的数据之间的相干性的方法和相应的装置。 更具体地说，该方法包括干扰测试，该干扰测试控制处理器单元从由无序加载指令识别的存储器中的相同位置读取数据，并将新读取的数据与保存在第一目的地寄存器中的数据进行比较 。 如果值不匹配，则新读取的数据被放置在第二目的寄存器中，并执行恢复序列。 第二目的地寄存器可以与第一目的地寄存器相同。 本发明适用于指令的静态和动态重新排序，并且可以使用指令或使用硬件资源来实现。

公开(公告)号：US08539188B2

公开(公告)日：2013-09-17

申请号：US12362329

申请日：2009-01-29

申请人： Mayan Moudgill ,  Vitaly Kalashnikov ,  Murugappan Senthilvelan ,  Umesh Srikantiah ,  Tak-po Li ,  Pablo Balzola

发明人： Mayan Moudgill ,  Vitaly Kalashnikov ,  Murugappan Senthilvelan ,  Umesh Srikantiah ,  Tak-po Li ,  Pablo Balzola

IPC分类号： G06F12/14

CPC分类号： G06F9/526 ,  G06F9/52

摘要： A method for providing at least one sequence of values to a plurality of processors is described. In the method, a sequence generator from one or more sequence generators is associated with a memory location. The sequence generator is configured to generate the at least one sequence of values. One or more read accesses of the memory location are enabled by a processor from the plurality of processors. In response to enabling the read access, the sequence generator is executed so that it returns a first value from the sequence of values to the processor. After executing the sequence generator, the sequence generator is advanced so that the next access generates a second value from the sequence of values. The second value is sequentially subsequent to the first value.

摘要翻译： 描述了一种用于向多个处理器提供至少一个值序列的方法。 在该方法中，来自一个或多个序列生成器的序列生成器与存储器位置相关联。 序列生成器被配置为生成至少一个值序列。 存储器位置的一个或多个读取访问由来自多个处理器的处理器启用。 响应于启用读取访问，序列生成器被执行，使得其从值序列返回到处理器的第一值。 在执行序列生成器之后，序列发生器被提前使得下一次访问从值序列生成第二个值。 第二个值依次在第一个值之后。

公开(公告)号：US08056064B2

公开(公告)日：2011-11-08

申请号：US11573563

申请日：2005-08-11

申请人： Mayan Moudgill ,  Vladimir Kotlyar

发明人： Mayan Moudgill ,  Vladimir Kotlyar

IPC分类号： G06F9/45

CPC分类号： G06F8/443

摘要： A method which determines by an optimizing compiler whether any variable in the given program equals to the given acyclic mathematical function applied to given variables in the program and the method includes expressing the bits of the value of the function as a Boolean function of the bits of the inputs and expressing for every variable and statement the value taken by v when s is executed as a Boolean function and expressing, for every statement the condition under which the statement is executed as a Boolean function, and Finally, a determination is made using a Boolean satisfiability oracle of whether, for the given variable and program statement, the a particular Boolean expression holds and a determination is of whether for a given variable and program statement whenever the predicate and the condition are true.

摘要翻译： 通过优化编译器确定给定程序中的任何变量是否等于应用于程序中的给定变量的给定非循环数学函数的方法，包括将函数的值的位表示为位的布尔函数 输入和表达每个变量，并陈述当s作为布尔函数执行时由v采取的值，并为每个语句表示语句作为布尔函数执行的条件，最后，使用 对于给定的变量和程序语句，对于特定的布尔表达式是否保持，并且当谓词和条件为真时，是否对给定的变量和程序语句确定是否为布尔可满足性oracle。

公开(公告)号：US07895413B2

公开(公告)日：2011-02-22

申请号：US12121564

申请日：2008-05-15

申请人： Mayan Moudgill

发明人： Mayan Moudgill

IPC分类号： G06F15/76

CPC分类号： G06F9/3012 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3885 ,  G06F9/3891

摘要： A microprocessor for processing instructions comprises multiple clusters for receiving the instructions, each of the clusters having a plurality of functional units for executing the instructions, multiple register sub-files each having multiple registers for storing data for executing the instructions, wherein each of the clusters is associated with corresponding one of the register sub-files so that an instruction dispatched to a cluster is executed by accessing registers in a register sub-file associated with the cluster to which the instruction is dispatched, a register-renaming unit for renaming target registers in an instruction with registers in a register sub-file associated with a cluster to which the instruction is dispatched, and issue-queue units each of which is associated with a corresponding one of the clusters, wherein an issue-queue unit holds instruction renamed by the register-renaming unit until the renamed instruction is issued to be executed in a cluster associated with the issue-queue unit.

摘要翻译： 用于处理指令的微处理器包括用于接收指令的多个簇，每个簇具有用于执行指令的多个功能单元，每个具有多个寄存器的多个寄存器子文件用于存储用于执行指令的数据，其中每个簇 与对应的一个寄存器子文件相关联，从而通过访问与分发指令的集群相关联的寄存器子文件中的寄存器来执行发送到集群的指令，用于重命名目标寄存器的寄存器重命名单元 在与分配了指令的集群相关联的寄存器子文件中的寄存器的指令和每个与对应的一个集群相关联的发布队列单元中，其中发布队列单元保存由 注册重命名单元，直到发出重命名的指令才能在集群关联中执行 d与问题队列单位。