公开(公告)号：US5905621A

公开(公告)日：1999-05-18

申请号：US4795

申请日：1998-01-09

申请人： Oleg Drapkin

发明人： Oleg Drapkin

IPC分类号： H03K19/003 ,  H02H3/20

CPC分类号： H03K19/00315

摘要： A voltage scaling circuit for protecting an input node to a protected circuit uses a voltage shifting circuit that includes two nmos transistors. One nmos transistor is configured as a bi-directional voltage follower and the other nmos transistor is configured as uni-directional voltage follower to facilitate input high level shifting between an input signal node, such as a pin of an integrated circuit and an input node to the protected circuit.

摘要翻译： 用于将输入节点保护到受保护电路的电压调节电路使用包括两个nmos晶体管的电压移位电路。 一个nmos晶体管被配置为双向电压跟随器，而另一个nmos晶体管被配置为单向电压跟随器，以便于诸如集成电路的引脚和输入节点之类的输入信号节点之间的输入高电平移位，以便 受保护的电路。

公开(公告)号：US07017070B1

公开(公告)日：2006-03-21

申请号：US09687858

申请日：2000-10-13

申请人： Chak Cheung Edward Ho ,  Oleg Drapkin ,  Carl Mizuyabu ,  Ray Chau ,  Gordon Caruk

发明人： Chak Cheung Edward Ho ,  Oleg Drapkin ,  Carl Mizuyabu ,  Ray Chau ,  Gordon Caruk

IPC分类号： G06F1/12 ,  G06F1/04

CPC分类号： G06F13/4243 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222

摘要： A signal phase shifting circuit shifts the phase of an input signal, such as a STROBE signal, based on a reference signal, such as a CLOCK signal, to facilitate, for example, receiving of double data rate data. The signal phase shifting circuit includes a reference signal period dividing circuit having a feedback delay matching array operatively coupled to one of a plurality of voltage control delay lines. This signal phase shifting circuit also includes a variable delay circuit that provides a phase shifted output signal, such as a phase shifted STROBE signal, that includes a delay stage in a phase shifted output signal drive buffer coupled to the delay stage, such as a voltage control delay line. The feedback delay matching array includes a plurality of serially coupled buffer stages operatively coupled to compensate for delay variations associated with the phase shifted output signal drive buffer in the variable delay circuit.

摘要翻译： 信号移相电路基于诸如CLOCK信号的参考信号来移动诸如STROBE信号的输入信号的相位，以便于例如接收双倍数据速率数据。 信号移相电路包括具有可操作地耦合到多个电压控制延迟线之一的反馈延迟匹配阵列的参考信号周期分频电路。 该信号移相电路还包括可变延迟电路，其提供相移输出信号，例如相移的STROBE信号，该相移输出信号包括耦合到延迟级的相移输出信号驱动缓冲器中的延迟级，例如电压 控制延时线。 反馈延迟匹配阵列包括可操作地耦合以补偿与可变延迟电路中的相移输出信号驱动缓冲器相关联的延迟变化的多个串联耦合缓冲器级。

公开(公告)号：US07106125B1

公开(公告)日：2006-09-12

申请号：US09651944

申请日：2000-08-31

申请人： Oleg Drapkin ,  Grigory Temkine

发明人： Oleg Drapkin ,  Grigory Temkine

IPC分类号： H03K17/16

CPC分类号： H04L25/0278

摘要： An input/output circuit in a receiving mode typically has disabled output buffers as well as other electrical components that provide significant receiver input capacities at high operating frequencies. A detection circuit detects the charging/discharging of the parasitic capacitance and operates a regulating circuit to compensate for the charging/discharging of the parasitic capacitance during rising/falling edges of an input signal, thereby correcting for impedance mismatch and reflection glitches.

摘要翻译： 接收模式下的输入/输出电路通常具有禁用的输出缓冲器以及在高工作频率下提供重要的接收机输入容量的其他电气部件。 检测电路检测寄生电容的充电/放电，并且操作调节电路以补偿输入信号的上升/下降沿期间的寄生电容的充电/放电，由此校正阻抗失配和反射毛刺。

公开(公告)号：US06532525B1

公开(公告)日：2003-03-11

申请号：US09675368

申请日：2000-09-29

申请人： Milivoje Aleksic ,  Grigory Temkine ,  Oleg Drapkin ,  Carl Mizuyabu ,  Adrian Hartog

发明人： Milivoje Aleksic ,  Grigory Temkine ,  Oleg Drapkin ,  Carl Mizuyabu ,  Adrian Hartog

IPC分类号： G06F1200

CPC分类号： G06F13/1689 ,  G09G5/39 ,  Y02D10/14

摘要： A specific embodiment is disclosed for a method and apparatus for processing data access requests from a requesting device, such as a graphics processor device. Data access commands are provided at a first rate, for example 200M commands per second, to a memory bridge. In response to receiving the access requests the memory bridge will provide its own access requests to a plurality of memories at approximately the first rate. In response to the memory bridge requests, the plurality of memories will access a plurality of data at a second data rate. When the data access between the memory bridge and the memories is a read request, data is returned to the requesting device at a third data rate which is greater than the first data rate by approximately four-times or more. Noise and power reduction techniques can be used on the data bus between the accessing device and the data bridge.

摘要翻译： 公开了一种用于处理来自请求设备（诸如图形处理器设备）的数据访问请求的方法和设备的具体实施例。 数据访问命令以第一速率（例如每秒200M命令）提供给存储器桥。 响应于接收到访问请求，存储器桥将以大约第一速率向多个存储器提供其自己的访问请求。 响应于存储器桥请求，多个存储器将以第二数据速率访问多个数据。 当存储器桥和存储器之间的数据访问是读取请求时，数据以大于第一数据速率的大约四倍或更多的第三数据速率返回给请求设备。 噪声和功率降低技术可以在接入设备和数据桥之间的数据总线上使用。

公开(公告)号：US06502173B1

公开(公告)日：2002-12-31

申请号：US09675293

申请日：2000-09-29

申请人： Milivoje Aleksic ,  Grigory Temkine ,  Oleg Drapkin ,  Carl Mizuyabu ,  Adrian Hartog

发明人： Milivoje Aleksic ,  Grigory Temkine ,  Oleg Drapkin ,  Carl Mizuyabu ,  Adrian Hartog

IPC分类号： G06F1200

CPC分类号： G06F13/1689 ,  G06F13/1605 ,  Y02D10/14

摘要： A specific embodiment is disclosed for a method and apparatus for processing data access requests from a requesting device, such as a graphics processor device. Data access commands are provided at a first rate, for example 200M command per second, to a memory bridge. In response to receiving the access requests the memory bridge will provide its own access requests to a plurality of memories at approximately the first rate. In response to the memory bridge requests, the plurality of memories will access a plurality of data a second data rate. When the data access between the memory bridge and the memories is a read request, data is returned to the requesting device at a third data rate which is greater than the first data rate by approximately four times or more. Noise and power reduction techniques can be used on the data bus between the accessing device and the data bridge.

摘要翻译： 公开了一种用于处理来自请求设备（诸如图形处理器设备）的数据访问请求的方法和设备的具体实施例。 数据访问命令以第一速率（例如每秒200M命令）提供给存储器桥。 响应于接收到访问请求，存储器桥将以大约第一速率向多个存储器提供其自己的访问请求。 响应于存储器桥请求，多个存储器将访问多个数据第二数据速率。 当存储器桥和存储器之间的数据访问是读取请求时，数据以大于第一数据速率的大约四倍或更多的第三数据速率返回给请求设备。 噪声和功率降低技术可以在接入设备和数据桥之间的数据总线上使用。