公开(公告)号：US07017070B1

公开(公告)日：2006-03-21

申请号：US09687858

申请日：2000-10-13

申请人： Chak Cheung Edward Ho ,  Oleg Drapkin ,  Carl Mizuyabu ,  Ray Chau ,  Gordon Caruk

发明人： Chak Cheung Edward Ho ,  Oleg Drapkin ,  Carl Mizuyabu ,  Ray Chau ,  Gordon Caruk

IPC分类号： G06F1/12 ,  G06F1/04

CPC分类号： G06F13/4243 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222

摘要： A signal phase shifting circuit shifts the phase of an input signal, such as a STROBE signal, based on a reference signal, such as a CLOCK signal, to facilitate, for example, receiving of double data rate data. The signal phase shifting circuit includes a reference signal period dividing circuit having a feedback delay matching array operatively coupled to one of a plurality of voltage control delay lines. This signal phase shifting circuit also includes a variable delay circuit that provides a phase shifted output signal, such as a phase shifted STROBE signal, that includes a delay stage in a phase shifted output signal drive buffer coupled to the delay stage, such as a voltage control delay line. The feedback delay matching array includes a plurality of serially coupled buffer stages operatively coupled to compensate for delay variations associated with the phase shifted output signal drive buffer in the variable delay circuit.

摘要翻译： 信号移相电路基于诸如CLOCK信号的参考信号来移动诸如STROBE信号的输入信号的相位，以便于例如接收双倍数据速率数据。 信号移相电路包括具有可操作地耦合到多个电压控制延迟线之一的反馈延迟匹配阵列的参考信号周期分频电路。 该信号移相电路还包括可变延迟电路，其提供相移输出信号，例如相移的STROBE信号，该相移输出信号包括耦合到延迟级的相移输出信号驱动缓冲器中的延迟级，例如电压 控制延时线。 反馈延迟匹配阵列包括可操作地耦合以补偿与可变延迟电路中的相移输出信号驱动缓冲器相关联的延迟变化的多个串联耦合缓冲器级。

公开(公告)号：US20060282604A1

公开(公告)日：2006-12-14

申请号：US11139733

申请日：2005-05-27

申请人： Grigori Temkine ,  Oleg Drapkin ,  Gordon Caruk

发明人： Grigori Temkine ,  Oleg Drapkin ,  Gordon Caruk

IPC分类号： G06F13/36

CPC分类号： G06T1/20 ,  G06T2200/28 ,  G06T2210/52 ,  G09G5/363

摘要： Methods and apparatus for providing multiple graphics processing capacity, while utilizing unused integrated graphics processing circuitry on a bridge circuit along with an external or discrete graphics processing unit is disclosed. In particular, a bridge circuit includes an integrated graphics processing circuit configured to process graphics jobs. The bridge circuit also includes an interface operable according to interface with a discrete graphics processing circuit. A controller is included with the bridge circuit and responsive whenever the discrete graphics processing circuit is coupled to the interface to cause the integrated graphics processing circuit to process a task of the graphics job in conjunction with operation of the discrete graphics processing circuit that is operable to process another task of the graphics job. Corresponding methods are also disclosed.

摘要翻译： 公开了一种用于提供多种图形处理能力的方法和装置，同时利用桥接电路上的未使用的集成图形处理电路以及外部或分立的图形处理单元。 特别地，桥接电路包括被配置为处理图形作业的集成图形处理电路。 桥接电路还包括根据与分立图形处理电路的接口可操作的接口。 控制器包括在桥接电路中，并且每当离散图形处理电路耦合到接口时响应，使得集成图形处理电路结合图形处理电路的任务结合可分离的图形处理电路 处理图形作业的另一个任务。 还公开了相应的方法。

公开(公告)号：US06918047B1

公开(公告)日：2005-07-12

申请号：US09657255

申请日：2000-09-07

申请人： Richard K. Sita ,  Carl Mizuyabu ,  Oleg Drapkin

发明人： Richard K. Sita ,  Carl Mizuyabu ,  Oleg Drapkin

IPC分类号： G06F1/10 ,  G06F1/12 ,  G06F13/00 ,  G11C7/10 ,  H03L7/081 ,  H04L7/04

CPC分类号： G11C7/222 ,  G06F1/10 ,  G06F1/12 ,  G11C7/1072 ,  H03L7/0812 ,  H04L7/0037

摘要： A reference signal input of a delay locked loop is connected to receive a reference clock. The delay locked loop provides a drive clock that drives a clock distribution tree. One of the endpoints of the clock distribution tree is connected to a feedback reference of the delay locked loop. By using one the endpoints as a feedback loop to the delay locked loop the signal received at components attached to the endpoints of the distribution tree can be synchronized to the reference input received at the delay locked loop.

摘要翻译： 连接延迟锁定环路的参考信号输入以接收参考时钟。 延迟锁定环路提供驱动时钟分配树的驱动器时钟。 时钟分配树的端点之一连接到延迟锁定环路的反馈参考。 通过使用一个端点作为延迟锁定环路的反馈回路，在分配树的端点附近的组件处接收到的信号可以被同步到在延迟锁定环路处接收到的参考输入。

公开(公告)号：US06532525B1

公开(公告)日：2003-03-11

申请号：US09675368

申请日：2000-09-29

申请人： Milivoje Aleksic ,  Grigory Temkine ,  Oleg Drapkin ,  Carl Mizuyabu ,  Adrian Hartog

发明人： Milivoje Aleksic ,  Grigory Temkine ,  Oleg Drapkin ,  Carl Mizuyabu ,  Adrian Hartog

IPC分类号： G06F1200

CPC分类号： G06F13/1689 ,  G09G5/39 ,  Y02D10/14

摘要： A specific embodiment is disclosed for a method and apparatus for processing data access requests from a requesting device, such as a graphics processor device. Data access commands are provided at a first rate, for example 200M commands per second, to a memory bridge. In response to receiving the access requests the memory bridge will provide its own access requests to a plurality of memories at approximately the first rate. In response to the memory bridge requests, the plurality of memories will access a plurality of data at a second data rate. When the data access between the memory bridge and the memories is a read request, data is returned to the requesting device at a third data rate which is greater than the first data rate by approximately four-times or more. Noise and power reduction techniques can be used on the data bus between the accessing device and the data bridge.

摘要翻译： 公开了一种用于处理来自请求设备（诸如图形处理器设备）的数据访问请求的方法和设备的具体实施例。 数据访问命令以第一速率（例如每秒200M命令）提供给存储器桥。 响应于接收到访问请求，存储器桥将以大约第一速率向多个存储器提供其自己的访问请求。 响应于存储器桥请求，多个存储器将以第二数据速率访问多个数据。 当存储器桥和存储器之间的数据访问是读取请求时，数据以大于第一数据速率的大约四倍或更多的第三数据速率返回给请求设备。 噪声和功率降低技术可以在接入设备和数据桥之间的数据总线上使用。

公开(公告)号：US06502173B1

公开(公告)日：2002-12-31

申请号：US09675293

申请日：2000-09-29

申请人： Milivoje Aleksic ,  Grigory Temkine ,  Oleg Drapkin ,  Carl Mizuyabu ,  Adrian Hartog

发明人： Milivoje Aleksic ,  Grigory Temkine ,  Oleg Drapkin ,  Carl Mizuyabu ,  Adrian Hartog

IPC分类号： G06F1200

CPC分类号： G06F13/1689 ,  G06F13/1605 ,  Y02D10/14

摘要： A specific embodiment is disclosed for a method and apparatus for processing data access requests from a requesting device, such as a graphics processor device. Data access commands are provided at a first rate, for example 200M command per second, to a memory bridge. In response to receiving the access requests the memory bridge will provide its own access requests to a plurality of memories at approximately the first rate. In response to the memory bridge requests, the plurality of memories will access a plurality of data a second data rate. When the data access between the memory bridge and the memories is a read request, data is returned to the requesting device at a third data rate which is greater than the first data rate by approximately four times or more. Noise and power reduction techniques can be used on the data bus between the accessing device and the data bridge.

摘要翻译： 公开了一种用于处理来自请求设备（诸如图形处理器设备）的数据访问请求的方法和设备的具体实施例。 数据访问命令以第一速率（例如每秒200M命令）提供给存储器桥。 响应于接收到访问请求，存储器桥将以大约第一速率向多个存储器提供其自己的访问请求。 响应于存储器桥请求，多个存储器将访问多个数据第二数据速率。 当存储器桥和存储器之间的数据访问是读取请求时，数据以大于第一数据速率的大约四倍或更多的第三数据速率返回给请求设备。 噪声和功率降低技术可以在接入设备和数据桥之间的数据总线上使用。

公开(公告)号：US08570067B2

公开(公告)日：2013-10-29

申请号：US11749002

申请日：2007-05-15

申请人： Oleg Drapkin ,  Grigori Temkine ,  Marcus Ng ,  Kevin Yikai Liang ,  Arvind Bomdica ,  Siji Menokki Kandiyil ,  Ming So ,  Samu Suryanarayana

发明人： Oleg Drapkin ,  Grigori Temkine ,  Marcus Ng ,  Kevin Yikai Liang ,  Arvind Bomdica ,  Siji Menokki Kandiyil ,  Ming So ,  Samu Suryanarayana

IPC分类号： H03K19/0175

CPC分类号： H03K19/00384 ,  H03K17/223 ,  H04L25/028

摘要： An integrated circuit is capable of controlling a communication signal by using power ramp controlled communication buffer logic to generate an outgoing communication signal based on a detected voltage on a voltage source. The voltage source is necessary to supply power for power ramp controlled communication buffer logic. The voltage on the voltage source may be detected using power ramp sensor logic. The outgoing communication signal is based on a core logic output signal if the detected voltage is greater than or equal to a predetermined voltage level. If, the detected voltage is less than the predetermined voltage level, the outgoing communication signal is predetermined to be one of: a tristate outgoing communication signal, a logic one outgoing communication signal and a logic zero outgoing communication signal. Power ramp controlled communication buffer logic may also generate a core logic input signal based on an incoming communication signal in response to the detected voltage.

摘要翻译： 集成电路能够通过使用功率斜坡控制的通信缓冲器逻辑来控制通信信号，以基于电压源上的检测到的电压来产生输出通信信号。 为电源斜坡控制的通信缓冲逻辑电源供电需要电压源。 可以使用功率斜坡传感器逻辑检测电压源上的电压。 如果检测到的电压大于或等于预定电压电平，则输出通信信号基于核心逻辑输出信号。 如果检测到的电压小于预定电压电平，则将输出通信信号预定为三态输出通信信号，逻辑1输出通信信号和逻辑零输出通信信号之一。 功率斜坡控制通信缓冲器逻辑还可以响应于检测到的电压而基于输入通信信号生成核心逻辑输入信号。

公开(公告)号：US20080157817A1

公开(公告)日：2008-07-03

申请号：US12046887

申请日：2008-03-12

申请人： Oleg Drapkin ,  Grigori Temkine ,  Arvind Bomdica ,  Kevin Liang

发明人： Oleg Drapkin ,  Grigori Temkine ,  Arvind Bomdica ,  Kevin Liang

IPC分类号： H03K19/0185

CPC分类号： H03K19/0185 ,  H03K19/094

摘要： An input signal is routed to a first logic one reference signal generator or alternatively routed to a second logic one reference signal generator based at least one a voltage level of the input signal. When the voltage level of the input signal is less than a threshold value, the first logic one reference signal generator selectively generates a first logic one reference signal. When the voltage level of the input signal is greater than or equal to the threshold value, the second logic one reference signal generator alternatively generates a second logic one reference signal. The first and second logic one reference signals may be used to control a first voltage scaling circuit that drives a scaled output signal having a logic one value corresponding to the voltage level of the first logic one reference signal.

摘要翻译： 输入信号被路由到第一逻辑一个参考信号发生器，或者基于输入信号的至少一个电压电平路由到第二逻辑1参考信号发生器。 当输入信号的电压电平小于阈值时，第一逻辑1参考信号发生器选择性地产生第一逻辑1参考信号。 当输入信号的电压电平大于或等于阈值时，第二逻辑1参考信号发生器交替产生第二逻辑1参考信号。 第一和第二逻辑一个参考信号可以用于控制驱动具有对应于第一逻辑1参考信号的电压电平的逻辑1值的定标输出信号的第一电压缩放电路。

公开(公告)号：US20060038620A1

公开(公告)日：2006-02-23

申请号：US10924145

申请日：2004-08-23

申请人： Oleg Drapkin ,  Grigori Temkine ,  Mikhail Rodionov ,  Michael Foxcroft

发明人： Oleg Drapkin ,  Grigori Temkine ,  Mikhail Rodionov ,  Michael Foxcroft

IPC分类号： H03L7/00

CPC分类号： H03L7/093 ,  H03L7/0891 ,  H03L7/18

摘要： A circuit includes a phase lock loop circuit and a continuous phase lock loop calibration circuit. The continuous phase lock loop calibration circuit is operatively coupled to the PLL circuit and produces a continuous calibration signal based on a reference voltage from a reference voltage circuit to calibrate the PLL circuit on a continuous basis.

摘要翻译： 电路包括锁相环电路和连续锁相环校准电路。 连续锁相环校准电路可操作地耦合到PLL电路，并且基于来自参考电压电路的参考电压产生连续校准信号，以连续地校准PLL电路。

公开(公告)号：US06373282B1

公开(公告)日：2002-04-16

申请号：US09379197

申请日：1999-08-20

申请人： Oleg Drapkin ,  Grigori Tempkine

发明人： Oleg Drapkin ,  Grigori Tempkine

IPC分类号： H03K19094

CPC分类号： H03K19/018507 ,  H03K19/00315

摘要： A cascaded output buffer stage and buffering method converts a voltage level of a received internal signal, such as a signal to be output (transmitted) from the cascaded output buffer stage, prior to outputting the received signal; selectively provides a variable reference voltage signal for a cascaded circuit element in the output buffer and also generates a floating well output signal for wells associated the cascaded upper buffer circuit elements. The cascaded output buffer stage is also, in one embodiment, a single gate oxide cascaded output buffer stage. In one embodiment, a voltage level shifting circuit is used along with a variable reference generating circuit that provides a variable reference voltage signal to cascaded output buffer circuits, and that also provides a floating well output signal to wells of the cascaded circuit. The voltage level shifting circuit and variable reference generating circuit is operatively coupled to a cascaded pull up circuit or cascaded pull down circuit as needed.

摘要翻译： 级联输出缓冲级和缓冲方法在输出接收到的信号之前，将所接收的内部信号的电压电平，例如要从级联输出缓冲级输出（发送）的信号转换; 选择性地为输出缓冲器中的级联电路元件提供可变参考电压信号，并且还产生用于与级联的上缓冲电路元件相关联的阱的浮置阱输出信号。 在一个实施例中，级联输出缓冲器级也是单栅极氧化级联输出缓冲级。 在一个实施例中，电压电平移位电路与可变参考产生电路一起使用，该可变参考产生电路向级联输出缓冲器电路提供可变参考电压信号，并且还向级联电路的阱提供浮置阱输出信号。 电压电平移动电路和可变参考产生电路根据需要可操作地耦合到级联上拉电路或级联下拉电路。

公开(公告)号：US06268744B1

公开(公告)日：2001-07-31

申请号：US09609022

申请日：2000-06-30

申请人： Oleg Drapkin ,  Grigori Temkine

发明人： Oleg Drapkin ,  Grigori Temkine

IPC分类号： H03K190185

CPC分类号： H03K19/00315 ,  H03K19/018585

摘要： A buffer circuit utilizes a single gate oxide pre-buffer voltage level shifting circuit on, for example, an output buffer of an I/O pad, to accommodate different I/O pad supply voltages while maintaining normal operating voltages (degradation levels) across boundaries of single gate oxide devices that form the buffer. The single gate oxide output buffer can operate at several different supply voltages. A pre-buffer voltage level shifting circuit includes a multi-supply voltage level shifting circuit having signal gate oxide devices coupled to produce a pre-buffer output signal to an output buffer. A single gate oxide cross coupled active load is coupled to the multi-supply voltage level shifting circuit and provides suitable drive voltages to at least one of cascaded buffer transistors.

摘要翻译： 缓冲电路在例如I / O焊盘的输出缓冲器上使用单栅极氧化物预缓冲器电压电平移位电路，以适应不同的I / O焊盘电源电压，同时保持跨越边界的正常工作电压（劣化电平） 的形成缓冲器的单栅极氧化物器件。 单栅极氧化物输出缓冲器可以在几种不同的电源电压下工作。 预缓冲器电压电平移位电路包括多电源电压移位电路，其具有被耦合以产生到缓冲器输出缓冲器的预缓冲器输出信号的信号栅极氧化器件。 单栅极氧化物交叉耦合有源负载耦合到多电源电压电平移位电路，并向级联缓冲晶体管中的至少一个提供合适的驱动电压。