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51.发明申请System and Method for Completing Full Updates to Entire Cache Lines Stores with Address-Only Bus Operations 有权完整的完整更新的系统和方法完整的缓存行存储仅地址总线操作公开(公告)号：US20080140943A1
公开(公告)日：2008-06-12
申请号：US12034769
申请日：2008-02-21
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0804
摘要： A method and processor system that substantially eliminates data bus operations when completing updates of an entire cache line with a full store queue entry. The store queue within a processor chip is designed with a series of AND gates connecting individual bits of the byte enable bits of a corresponding entry. The AND output is fed to the STQ controller and signals when the entry is full. When full entries are selected for dispatch to the RC machines, the RC machine is signaled that the entry updates the entire cache line. The RC machine obtains write permission to the line, and then the RC machine overwrites the entire cache line. Because the entire cache line is overwritten, the data of the cache line is not retrieved when the request for the cache line misses at the cache or when data goes state before write permission is obtained by the RC machine.
摘要翻译： 一种方法和处理器系统，其在完成具有完整存储队列条目的整个高速缓存行的更新时基本上消除数据总线操作。 处理器芯片内的存储队列设计有连接相应条目的字节使能位的各个位的一系列与门。 AND输出被馈送到STQ控制器，并在条目已满时发出信号。 当选择完整条目以发送到RC机器时，RC机器发出信号，表示该条目更新整个高速缓存行。 RC机器获得线路的写入权限，然后RC机器覆盖整个高速缓存行。 由于整个高速缓存线被覆盖，当缓存线的请求在高速缓存中丢失或数据在RC写入权限获得之前状态时，不会检索高速缓存行的数据。
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52.发明申请Method for Priority Scheduling and Priority Dispatching of Store Conditional Operations in a Store Queue 有权存储队列中存储条件操作优先级调度和优先调度的方法公开(公告)号：US20080140936A1
公开(公告)日：2008-06-12
申请号：US12033441
申请日：2008-02-19
IPC分类号： G06F12/08
CPC分类号： G06F9/30087 , G06F9/3004 , G06F9/3824 , G06F9/3834 , G06F9/3851
摘要： A method, system, and processor chip design for reducing the latency between completing a LARX operation and receiving the associated STCX operation to complete the update to the cache line. Each entry of the store queue of the issuing processor is provided an additional tracking bit (priority bit). The priority bit is set whenever a STCX operation is placed within the entry. During selection of an entry for dispatch by the arbitration logic, the arbitration logic scans the value of the priority bits of each eligible entry. An entry with the priority bit set is given priority in the selection process within architectural rules. That entry is then selected for dispatch as early as is possible within the established rules.
摘要翻译： 一种方法，系统和处理器芯片设计，用于减少完成LARX操作和接收相关联的STCX操作之间的延迟，以完成对高速缓存行的更新。 向发行处理器的存储队列的每个条目提供附加跟踪位（优先级位）。 每当在条目中放置STCX操作时，优先级位置位。 在选择由仲裁逻辑发送的条目期间，仲裁逻辑扫描每个合格条目的优先级位的值。 具有优先级位的条目在架构规则中的选择过程中被赋予优先级。 然后在既定规则内尽可能早地选择该条目进行发送。
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53.发明授权Processor, method, and data processing system employing a variable store gather window 有权处理器，方法和数据处理系统采用变量存储收集窗口公开(公告)号：US07366851B2
公开(公告)日：2008-04-29
申请号：US10922272
申请日：2004-08-19
IPC分类号： G06F12/08
CPC分类号： G06F9/3824 , G06F9/30043 , G06F12/0897
摘要： A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue includes a queue entry in which the store queue gathers multiple store operations during a store gathering window to obtain a data portion of a write transaction directed to lower level memory. In addition, the store queue includes dispatch logic that varies a size of the store gathering window to optimize store performance for different store behaviors and workloads.
摘要翻译： 处理器包括执行存储指令以获得存储操作的至少一个指令执行单元和耦合到指令执行单元的存储队列。 存储队列包括队列条目，其中存储队列在存储收集窗口期间收集多个存储操作，以获得指向低级存储器的写入事务的数据部分。 此外，商店队列包括调度逻辑，其改变商店收集窗口的大小以优化针对不同商店行为和工作负载的存储性能。
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54.发明申请公开(公告)号：US20060179226A1
公开(公告)日：2006-08-10
申请号：US11054450
申请日：2005-02-09
申请人： Guy Guthrie , Hugh Shen , William Starke , Derek Williams
发明人： Guy Guthrie , Hugh Shen , William Starke , Derek Williams
IPC分类号： G06F12/00
CPC分类号： G06F9/3834 , G06F9/30043 , G06F9/3824 , G06F12/0817
摘要： A system and method for re-ordering store operations from a processor core to a store queue. When a store queue receives a new processor-issued store operation from the processor core, a store queue controller allocates a new entry in the store queue. In response to allocating the new entry in the store queue, the store queue controller determines whether or not the new entry is dependent on at least one other valid entry in the store queue. In response to determining the new entry is dependent on at least one other valid entry in the store queue, the store queue controller inhibits requesting of the new entry to the RC dispatch logic until each valid entry on which the new entry is dependent has been successfully dispatched to an RC machine by the RC dispatch logic.
摘要翻译： 一种用于重新排序从处理器核到存储队列的存储操作的系统和方法。 当存储队列从处理器核心接收到新的处理器发出的存储操作时，存储队列控制器在存储队列中分配新的条目。 响应于在商店队列中分配新条目，商店队列控制器确定新条目是否依赖于商店队列中的至少一个其他有效条目。 响应于确定新条目取决于存储队列中的至少一个其他有效条目，存储队列控制器禁止向RC调度逻辑请求新条目，直到新条目依赖于其上的每个有效条目已经成功 通过RC调度逻辑调度到RC机器。
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55.发明授权System and method to stall dispatch of gathered store operations in a store queue using a timer 失效使用定时器将存储队列中收集的存储操作分派的系统和方法停止公开(公告)号：US07089364B2
公开(公告)日：2006-08-08
申请号：US10825188
申请日：2004-04-15
IPC分类号： G06F12/12
CPC分类号： G06F12/0897 , G06F9/30043 , G06F9/3824 , G06F9/3834 , G06F12/0804
摘要： A method and processor system that substantially enhances the store gathering capabilities of a store queue entry to enable gathering of a maximum number of proximate-in-time store operations before the entry is selected for dispatch. A counter is provided for each entry to track a time since a last gather to the entry. When a new gather does not occur before the counter reaches a threshold saturation point, the entry is signaled ready for dispatch. By defining an optimum threshold saturation point before the counter expires, sufficient time is provided for the entry to gather a proximate-in-time store operation. The entry may be deemed eligible for selection when certain conditions occur, including the entry becoming full, issuance of a barrier operation, and saturation of the counter. The use of the counter increases the ability of a store queue entry to complete gathering of enough store operations to update an entire cache line before that entry is dispatched to an RC machine.
摘要翻译： 一种方法和处理器系统，其基本上增强了存储队列条目的存储收集能力，以便能够在该条目被选择用于发送之前收集最大数量的接近时间存储操作。 为每个条目提供一个计数器，以跟踪从上次收集到条目的时间。 当计数器达到阈值饱和点之前没有发生新的聚合时，该信号将被发出准备就绪。 通过在计数器到期之前定义最佳阈值饱和点，为入口提供足够的时间来收集即时存储操作。 当某些条件发生时，该条目可能被视为有资格进行选择，包括条目变满，发出屏障操作和计数器饱和。 计数器的使用增加了存储队列条目完成收集足够的存储操作以在将该条目分派到RC机器之前更新整个高速缓存行的能力。
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56.发明申请Processor, method, and data processing system employing a variable store gather window 有权处理器，方法和数据处理系统采用变量存储收集窗口公开(公告)号：US20060095691A1
公开(公告)日：2006-05-04
申请号：US10922272
申请日：2004-08-19
申请人： Robert Bell , Hugh Shen , Jeffrey Stuecheli , Derek Williams
发明人： Robert Bell , Hugh Shen , Jeffrey Stuecheli , Derek Williams
IPC分类号： G06F12/00
CPC分类号： G06F9/3824 , G06F9/30043 , G06F12/0897
摘要： A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue includes a queue entry in which the store queue gathers multiple store operations during a store gathering window to obtain a data portion of a write transaction directed to lower level memory. In addition, the store queue includes dispatch logic that varies a size of the store gathering window to optimize store performance for different store behaviors and workloads.
摘要翻译： 处理器包括执行存储指令以获得存储操作的至少一个指令执行单元和耦合到指令执行单元的存储队列。 存储队列包括队列条目，其中存储队列在存储收集窗口期间收集多个存储操作，以获得指向低级存储器的写入事务的数据部分。 此外，商店队列包括调度逻辑，其改变商店收集窗口的大小以优化针对不同商店行为和工作负载的存储性能。
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57.发明申请Method for completing full cacheline stores with address-only bus operations 有权完成具有仅地址总线操作的完整缓存线存储的方法公开(公告)号：US20050251623A1
公开(公告)日：2005-11-10
申请号：US10825189
申请日：2004-04-15
申请人： Ravi Arimilli , Guy Guthrie , Hugh Shen , Derek Williams
发明人： Ravi Arimilli , Guy Guthrie , Hugh Shen , Derek Williams
CPC分类号： G06F12/0897 , G06F12/0804
摘要： A method and processor system that substantially eliminates data bus operations when completing updates of an entire cache line with a full store queue entry. The store queue within a processor chip is designed with a series of AND gates connecting individual bits of the byte enable bits of a corresponding entry. The AND output is fed to the STQ controller and signals when the entry is full. When full entries are selected for dispatch to the RC machines, the RC machine is signaled that the entry updates the entire cache line. The RC machine obtains write permission to the line, and then the RC machine overwrites the entire cache line. Because the entire cache line is overwritten, the data of the cache line is not retrieved when the request for the cache line misses at the cache or when data goes state before write permission is obtained by the RC machine.
摘要翻译： 一种方法和处理器系统，其在完成具有完整存储队列条目的整个高速缓存行的更新时基本上消除数据总线操作。 处理器芯片内的存储队列设计有连接相应条目的字节使能位的各个位的一系列与门。 AND输出被馈送到STQ控制器，并在条目已满时发出信号。 当选择完整条目以发送到RC机器时，RC机器发出信号，表示该条目更新整个高速缓存行。 RC机器获得线路的写入权限，然后RC机器覆盖整个高速缓存行。 由于整个高速缓存线被覆盖，当缓存线的请求在高速缓存中丢失时或在RC机器获得写入许可之前数据进入状态时，不会检索高速缓存行的数据。
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