-
公开(公告)号：US11861429B2
公开(公告)日：2024-01-02
申请号：US17049031
申请日：2018-04-30
Applicant: Hewlett Packard Enterprise Development LP
Inventor： John Paul Strachan , Dejan S. Milojicic , Martin Foltin , Sai Rahul Chalamalasetti , Amit S. Sharma
Abstract: In some examples, a device includes a first processing core comprising a resistive memory array to perform an analog computation, and a digital processing core comprising a digital memory programmable with different values to perform different computations responsive to respective different conditions. The device further includes a controller to selectively apply input data to the first processing core and the digital processing core.
-
公开(公告)号：US20230307048A1
公开(公告)日：2023-09-28
申请号：US18326813
申请日：2023-05-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Can Li , Catherine Graves , John Paul Strachan
Abstract: Systems are methods are provided for implementing an analog content addressable memory (analog CAM), which is particularly structured to allow for an amount of variance (fuzziness) in its search operations. The analog CAM may search for approximate matches with the data stored therein, or matches within a defined variance. Circuitry of the analog CAM may include transistor-source lines that receive search-variance parameters, and/or data lines that receive search-variance parameters explicitly within the search input data. The search-variance parameters may include an upper bound and a lower bound that define a range of values within the allotted amount of fuzziness (e.g., deviation from the stored value). The search-variance parameters may program (using analog approaches) the analog CAM to perform searches having a modifiable restrictiveness that is tuned dynamically, as defined by the input search-variance. Thus, highly efficient hardware for complex applications involving fuzziness are enabled.
-
公开(公告)号：US11580411B2
公开(公告)日：2023-02-14
申请号：US16224145
申请日：2018-12-18
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Suhas Kumar , Thomas Van Vaerenbergh , John Paul Strachan
Abstract: Systems are provided for implementing a hardware accelerator. The hardware accelerator emulate a stochastic neural network, and includes a first memristor crossbar array, and a second memristor crossbar array. The first memristor crossbar array can be programmed to calculate node values of the neural network. The nodes values can be calculated in accordance with rules to reduce an energy function associated with the neural network. The second memristor crossbar array is coupled to the first memristor crossbar array and programmed to introduce noise signals into the neural network. The noise signals can be introduced such that the energy function associated with the neural network converges towards a global minimum and modifies the calculated node values.
-
54.发明授权公开(公告)号：US11551771B2
公开(公告)日：2023-01-10
申请号：US17326223
申请日：2021-05-20
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： John Paul Strachan , Can Li , Catherine Graves
Abstract: Systems, devices, circuits, methods, and non-transitory computer readable media that enable storing and searching arbitrary segments of ranges of analog values are disclosed. Various analog content addressable memory (aCAM) circuit implementations having the capability to store and search outside of a range of values, within any of multiple disjoint ranges, or outside of multiple ranges are disclosed. The disclosed aCAM circuit implementations make searching for complex input features more flexible and efficient, thereby yielding a technological improvement over conventional solutions. In some implementations, an aCAM may include multiple pull-down transistors connected in series to a match line that is pre-charged, in which case, the aCAM detects a match if the match line is not discharged by the pull-down transistors, which occurs if at least one pull-down transistor is in an OFF state. In other implementations, an aCAM includes pass gates connected to a match line to detect a match.
-
55.发明申请公开(公告)号：US20220375536A1
公开(公告)日：2022-11-24
申请号：US17326223
申请日：2021-05-20
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： John Paul Strachan , Can Li , Catherine Graves
Abstract: Systems, devices, circuits, methods, and non-transitory computer readable media that enable storing and searching arbitrary segments of ranges of analog values are disclosed. Various analog content addressable memory (aCAM) circuit implementations having the capability to store and search outside of a range of values, within any of multiple disjoint ranges, or outside of multiple ranges are disclosed. The disclosed aCAM circuit implementations make searching for complex input features more flexible and efficient, thereby yielding a technological improvement over conventional solutions. In some implementations, an aCAM may include multiple pull-down transistors connected in series to a match line that is pre-charged, in which case, the aCAM detects a match if the match line is not discharged by the pull-down transistors, which occurs if at least one pull-down transistor is in an OFF state. In other implementations, an aCAM includes pass gates connected to a match line to detect a match.
-
Patent Agency Ranking
公开(公告)号：US11322545B2
公开(公告)日：2022-05-03
申请号：US17041382
申请日：2018-04-27
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Amit S. Sharma , John Paul Strachan , Martin Foltin
IPC: H01L29/66 , H01L21/02 , H01L27/24 , H01L29/161 , H01L29/808
Abstract: Devices and methods are provided. In one aspect, a device for driving a memristor array includes a substrate including a well having a bottom layer, a first wall and a second wall. The substrate is formed of a strained layer of a first semiconductor material. A vertical JFET is formed in the well. The vertical JFET includes a vertical gate region formed in a middle portion of the well with a gate region height less than a depth of the well. A channel region is formed of an epitaxial layer of a second semiconductor wrapped around the vertical gate region. Vertical source regions are formed on both sides of a first end of the vertical gate region, and vertical drain regions are formed on both sides of a second end of the vertical gate region.
-
公开(公告)号：US11316537B2
公开(公告)日：2022-04-26
申请号：US16429983
申请日：2019-06-03
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Ron Roth , John Paul Strachan
Abstract: A fault-tolerant analog computing device includes a crossbar array having a number l rows and a number n columns intersecting the l rows to form l×n memory locations. The l rows of the crossbar array receive an input signal as a vector of length l. The n columns output an output signal as a vector of length n that is a dot product of the input signal and the matrix values defined in the l×n memory locations. Each memory location is programmed with a matrix value. A first set of k columns of the n columns is programmed with continuous analog target matrix values with which the input signal is to be multiplied, where k
-
58.发明申请公开(公告)号：US20220122646A1
公开(公告)日：2022-04-21
申请号：US17071924
申请日：2020-10-15
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Catherine Graves , Can Li , Kivanc Ozonat , John Paul Strachan
IPC: G11C11/00 , G11C11/412 , G11C11/06 , G06F9/38
Abstract: Examples described herein relate to a decision tree computation system in which a hardware accelerator for a decision tree is implemented in the form of an analog Content Addressable Memory (a-CAM) array. The hardware accelerator accesses a decision tree. The decision tree comprises of multiple paths and each path of the multiple paths includes a set of nodes. Each node of the decision tree is associated with a feature variable of multiple feature variables of the decision tree. The hardware accelerator combines multiple nodes among the set of nodes with a same feature variable into a combined single node. Wildcard values are replaced for feature variables not being evaluated in each path. Each combined single node associated with each feature variable is mapped to a corresponding column in the a-CAM array and the multiple paths of the decision tree to rows of the a-CAM array.
-
公开(公告)号：US20220069541A1
公开(公告)日：2022-03-03
申请号：US17004955
申请日：2020-08-27
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Bassem Tossoun , Di Liang , John Paul Strachan
Abstract: An optical device includes a light-emitting device integrated with a memory device. The memory device include a first electrode and a second electrode, and the light-emitting device includes a third electrode and the second electrode. In such configuration, a first voltage between the second electrode and the third electrode causes the light-emitting device to emit light of a first wavelength, and a second voltage between the first electrode and the second electrode while the memory device is at OFF state causes the light-emitting device to emit light of a second wavelength shorter than the first wavelength or while the memory device is at ON state causes the light-emitting device to emit light of a third wavelength longer than the first wavelength.
-
公开(公告)号：US20210343341A1
公开(公告)日：2021-11-04
申请号：US16862997
申请日：2020-04-30
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： John Paul Strachan , Catherine Graves , Can Li
IPC: G11C15/04
Abstract: An analog content addressable memory cell includes a match line, a high side, and a low side. The high side encodes a high bound on a range of values and includes a first three terminal memory device. The first three terminal memory device includes a first gate that sets a high voltage bound of the first three terminal memory device. Specifically, an input voltage applied at the first gate of the first memory device, if higher than the high voltage bound, turns the first memory device ON which discharges the match line. Similarly, the low side encodes a lower bound on a range of values and includes a second three terminal memory device. The second three terminal memory device includes a second gate that sets a low voltage bound of the second three terminal memory device. Specifically, an input voltage applied at the second gate of the second memory device, if lower than the low voltage bound, turns the first memory device ON which discharges the match line.
-
-
-
-
-
-
-
-
-
Search Results
146
records
(took 0.029 seconds)
