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202 条记录 (耗时 0.025 秒)

    INDUCTION COIL, A PLASMA GENERATOR AND A PLASMA GENERATING METHOD
    51.
    发明申请
    INDUCTION COIL, A PLASMA GENERATOR AND A PLASMA GENERATING METHOD 有权
    感应线圈，等离子体发生器和等离子体发生方法

    公开(公告)号：US20090278459A1

    公开(公告)日：2009-11-12

    申请号：US12509434

    申请日：2009-07-24

    申请人： Georgy K. Vinogradov ,  Vladimir M. Menagarishvili ,  Tetsuhiko Shimamura ,  Masayuki Nakamura

    发明人： Georgy K. Vinogradov ,  Vladimir M. Menagarishvili ,  Tetsuhiko Shimamura ,  Masayuki Nakamura

    IPC分类号： H05H1/24 ,  H01F27/29

    CPC分类号： H05H1/46 ,  H01J37/321 ,  H01J37/3211

    摘要： The plasma generator of our invention comprises of the induction coil which is symmetric with respect to the reference plane between two terminal ends. Plasma processing gas is supplied to a predetermined space, and high frequency electricity is supplied to the induction coil, thereby the plasma generator generates plasma in the space. The reference plane passes between the two terminal ends and through longitude axis of the induction coil. The plasma generator can generate plasma with high quality of homogeneous.

    摘要翻译： 本发明的等离子体发生器包括感应线圈，其相对于两个终端之间的参考平面对称。 将等离子体处理气体供给到规定的空间，向感应线圈供给高频电力，等离子体发生器在该空间中产生等离子体。 参考平面通过两个终端之间并通过感应线圈的经度轴。 等离子体发生器可以产生质量均匀的等离子体。

    Semiconductor memory device
    52.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US07609572B2

    公开(公告)日：2009-10-27

    申请号：US11963831

    申请日：2007-12-22

    申请人： Hiroaki Nakaya ,  Riichiro Takemura ,  Satoru Akiyama ,  Tomonori Sekiguchi ,  Masayuki Nakamura ,  Shinichi Miyatake

    发明人： Hiroaki Nakaya ,  Riichiro Takemura ,  Satoru Akiyama ,  Tomonori Sekiguchi ,  Masayuki Nakamura ,  Shinichi Miyatake

    IPC分类号： G11C7/00

    CPC分类号： G11C11/4091 ,  G11C7/08 ,  G11C2207/005

    摘要： In a semiconductor memory device, with respect to low voltage application, technique of controlling a gate voltage of a shared MOS transistor increasing sense speed and increasing data read speed by preventing data inversion caused by noise and reducing bit line capacitance during sensing is provided. By a shared MOS transistor gate voltage control circuit connecting a sense amplifier and a memory cell array, a shared MOS transistor gate voltage (SHR) is lowered in two stages and bit line capacitance to be amplified is reduced taking noise during the sensing into consideration so that the sense speed is increased. Therefore, a timing of activating a column selection signal can be hastened and as a result, data read time can be reduced.

    摘要翻译： 在半导体存储器件中，关于低电压应用，提供了通过防止由噪声引起的数据反转和降低感测期间的位线电容来控制共享MOS晶体管的栅极电压提高感测速度并增加数据读取速度的技术。 通过连接读出放大器和存储单元阵列的共享MOS晶体管栅极电压控制电路，共享的MOS晶体管栅极电压（SHR）分为两级降低，并且在感测期间考虑到噪声，放大的位线电容降低 感觉速度增加。 因此，可以加快激活列选择信号的定时，结果可以减少数据读取时间。

    Pipe having enlarged and reduced diameters, and ejector using thereof
    55.
    发明申请
    Pipe having enlarged and reduced diameters, and ejector using thereof 审中-公开
    具有放大和缩小直径的管，以及使用其的喷射器

    公开(公告)号：US20060119101A1

    公开(公告)日：2006-06-08

    申请号：US11270255

    申请日：2005-11-09

    申请人： Yukio Suzuki ,  Masayuki Nakamura

    发明人： Yukio Suzuki ,  Masayuki Nakamura

    IPC分类号： F16L21/00

    CPC分类号： F16L9/006 ,  F25B2341/0012 ,  F25B2500/01

    摘要： A pipe may have enlarged and reduced diameters, which has low costs and which can prevent leakage of a fluid such as a refrigerant from the pipe even in such a configuration that a reduced diameter portion is continuous to an enlarged diameter portion continuous to another reduced diameter portion, the pipe being integrally and continuously formed by plastic or malleable working so as to having outer diameters (D1 . . . D8) which are longitudinally different from one another, and accordingly, the reduced diameter portion (1b-1c) being continuous to the enlarged diameter portion (1c-1d) which is continuous to another reduced diameter portion (1d-1e).

    摘要翻译： 管道可以具有扩大和减小的直径，其成本低，并且可以防止诸如制冷剂的流体从管道泄漏，即使是直径减小的部分连续到与另一直径相连的扩大直径部分的构造 所述管通过塑料或有延展性的工作一体地连续地形成，以具有彼此纵向不同的外径（D1 ... D8），因此，所述直径减小部分（1b-1c）为 连续到与另一直径减小部分（1d-1e）连续的扩大直径部分（1c-1d）。

    Redundancy semiconductor memory device with error correction code (ECC) circuits for correcting errors in recovery fuse data
    59.
    发明授权
    Redundancy semiconductor memory device with error correction code (ECC) circuits for correcting errors in recovery fuse data 失效
    具有用于校正恢复熔丝数据中的错误的纠错码（ECC）电路的冗余半导体存储器件

    公开(公告)号：US06915476B2

    公开(公告)日：2005-07-05

    申请号：US11004799

    申请日：2004-12-07

    申请人： Makoto Morino ,  Masayuki Nakamura

    发明人： Makoto Morino ,  Masayuki Nakamura

    IPC分类号： G11C29/04 ,  G06F11/10 ,  G11C7/00 ,  G11C11/401 ,  G11C29/00 ,  G11C29/42

    CPC分类号： G06F11/1008 ,  G11C29/789 ,  G11C29/802 ,  G11C29/812

    摘要： A semiconductor integrated circuit device includes a memory array having first to Nth banks, where N is an integer greater than or equal to 2. The memory array further includes a redundancy block having first to Nth column recovery circuit blocks corresponding to the first to Nth banks, first to Nth row recovery circuit blocks corresponding to the first to Nth banks, first to Nth ECC fuse blocks corresponding to the first to Nth banks, and first to Nth ECC circuits corresponding to the first to Nth banks. During initial cycles, the first to Nth ECC circuits correct errors in column recovery fuse data in the first to Nth column recovery circuit blocks and errors in row recovery fuse data in the first to Nth row recovery circuit blocks by using ECC fuse data in the first to Nth ECC fuse blocks, respectively.

    摘要翻译： 半导体集成电路装置包括具有第一至第N个存储体的存储器阵列，其中N是大于或等于2的整数。存储器阵列还包括具有与第一至第N个存储体相对应的第一至第N列恢复电路块的冗余块 对应于第一至第N组的第一至第N行恢复电路块，对应于第一至第N个存储体的第一至第N个ECC熔丝块以及对应于第一至第N个存储体的第一至第N个ECC电路。 在初始周期期间，第一至第N ECC电路通过在第一至第N行ECC恢复电路块中的第一至第N列恢复电路块中的ECC恢复熔丝数据和第一至第N行恢复电路块中的ECC恢复熔丝数据中的错误来校正第一至第N行恢复电路块中的ECC熔丝数据 到第N个ECC保险丝块。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    60.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
    半导体集成电路设备

    公开(公告)号：US20050122800A1

    公开(公告)日：2005-06-09

    申请号：US11004799

    申请日：2004-12-07

    申请人： Makoto Morino ,  Masayuki Nakamura

    发明人： Makoto Morino ,  Masayuki Nakamura

    IPC分类号： G11C29/04 ,  G06F11/10 ,  G11C7/00 ,  G11C11/401 ,  G11C29/00 ,  G11C29/42

    CPC分类号： G06F11/1008 ,  G11C29/789 ,  G11C29/802 ,  G11C29/812

    摘要： A semiconductor integrated circuit device includes a memory array having first to Nth banks, where N is an integer greater than or equal to 2. The memory array further includes a redundancy block having first to Nth column recovery circuit blocks corresponding to the first to Nth banks, first to Nth row recovery circuit blocks corresponding to the first to Nth banks, first to Nth ECC fuse blocks corresponding to the first to Nth banks, and first to Nth ECC circuits corresponding to the first to Nth banks. During initial cycles, the first to Nth ECC circuits correct errors in column recovery fuse data in the first to Nth column recovery circuit blocks and errors in row recovery fuse data in the first to Nth row recovery circuit blocks by using ECC fuse data in the first to Nth ECC fuse blocks, respectively.

    摘要翻译： 半导体集成电路装置包括具有第一至第N个存储体的存储器阵列，其中N是大于或等于2的整数。存储器阵列还包括具有与第一至第N个存储体相对应的第一至第N列恢复电路块的冗余块 对应于第一至第N组的第一至第N行恢复电路块，对应于第一至第N个存储体的第一至第N个ECC熔丝块以及对应于第一至第N个存储体的第一至第N个ECC电路。 在初始周期期间，第一至第N ECC电路通过在第一至第N行ECC恢复电路块中的第一至第N列恢复电路块中的ECC恢复熔丝数据和第一至第N行恢复电路块中的ECC恢复熔丝数据中的错误来校正第一至第N行恢复电路块中的ECC熔丝数据 到第N个ECC保险丝块。