公开(公告)号：US20190286567A1

公开(公告)日：2019-09-19

申请号：US15923174

申请日：2018-03-16

Applicant: Intel Corporation

Inventor： Mainak Chaudhuri ,  Jayesh Gaur ,  Sreenivas Subramoney ,  Hong Wang

IPC: G06F12/0895 ,  G06F12/0891 ,  G06F12/0804 ,  G06F12/12

Abstract: In one embodiment, a processor includes: a cache memory to store a plurality of cache lines; and a cache controller to control the cache memory. The cache controller may include a control circuit to allocate a virtual write buffer within the cache memory in response to a bandwidth on an interconnect that exceeds a first bandwidth threshold. The cache controller may further include a replacement circuit to control eviction of cache lines from the cache memory. Other embodiments are described and claimed.

公开(公告)号：US10162756B2

公开(公告)日：2018-12-25

申请号：US15408731

申请日：2017-01-18

Applicant: Intel Corporation

Inventor： Jayesh Gaur ,  Ayan Mandal ,  Anant Nori ,  Sreenivas Subramoney

IPC: G06F12/08 ,  G06F12/0811

Abstract: A memory-efficient last level cache (LLC) architecture is described. A processor implementing a LLC architecture may include a processor core, a last level cache (LLC) operatively coupled to the processor core, and a cache controller operatively coupled to the LLC. The cache controller is to monitor a bandwidth demand of a channel between the processor core and a dynamic random-access memory (DRAM) device associated with the LLC. The cache controller is further to perform a first defined number of consecutive reads from the DRAM device when the bandwidth demand exceeds a first threshold value and perform a first defined number of consecutive writes of modified lines from the LLC to the DRAM device when the bandwidth demand exceeds the first threshold value.

公开(公告)号：US10013352B2

公开(公告)日：2018-07-03

申请号：US14498963

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Sreenivas Subramoney ,  Jayesh Gaur ,  Mukesh Agrawal ,  Mainak Chaudhuri

IPC: G06F12/12 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0842 ,  G06F12/123

CPC classification number: G06F12/0811 ,  G06F12/0813 ,  G06F12/0842 ,  G06F12/123 ,  G06F2212/1024 ,  G06F2212/1056 ,  G06F2212/3042

Abstract: Embodiments described include systems, apparatuses, and methods using sectored dynamic random access memory (DRAM) cache. An exemplary apparatus may include at least one hardware processor core and a sectored dynamic random access (DRAM) cache coupled to the at least one hardware processor core.

公开(公告)号：US09251096B2

公开(公告)日：2016-02-02

申请号：US14036673

申请日：2013-09-25

Applicant: Intel Corporation

Inventor： Sreenivas Subramoney ,  Jayesh Gaur ,  Alaa R Alameldeen

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/126 ,  G06F12/0895

Abstract: In an embodiment, a processor includes a cache data array including a plurality of physical ways, each physical way to store a baseline way and a victim way; a cache tag array including a plurality of tag groups, each tag group associated with a particular physical way and including a first tag associated with the baseline way stored in the particular physical way, and a second tag associated with the victim way stored in the particular physical way; and cache control logic to: select a first baseline way based on a replacement policy, select a first victim way based on an available capacity of a first physical way including the first victim way, and move a first data element from the first baseline way to the first victim way. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括高速缓存数据阵列，其包括多个物理方式，每种物理方式来存储基线方式和受害方式; 包括多个标签组的缓存标签阵列，与特定物理方式相关联的每个标签组，并且包括与以特定物理方式存储的基线方式相关联的第一标签，以及与存储在特定物理方式中的受害方式相关联的第二标签 物理方式 以及高速缓存控制逻辑，以：基于替换策略选择第一基线方式，基于包括所述第一受害者方式的第一物理方式的可用容量选择第一受害者方式，并将第一数据元素从所述第一基线方式移动到 第一个受害者的方式。 描述和要求保护其他实施例。