公开(公告)号：US20220368537A1

公开(公告)日：2022-11-17

申请号：US17816148

申请日：2022-07-29

Applicant: Intel Corporation

Inventor： Manoj Sastry ,  Rafael Misoczki ,  Jordan Loney ,  David M. Wheeler

IPC: H04L9/32 ,  G06F21/72

Abstract: In one example an apparatus comprises a computer readable memory, a signing facility comprising a plurality of hardware security modules, and a state synchronization manager comprising processing circuitry to select, from the plurality of hardware security modules, a set of hardware security modules to be assigned to a digital signature process, the set of hardware security modules comprising at least a first hardware security module and a second hardware module, and assign a set of unique state synchronization counter sequences to the respective set of hardware security modules, the set of state synchronization counter sequences comprising at least a first state synchronization counter sequence and a second state synchronization counter sequence. Other examples may be described.

公开(公告)号：US20220353652A1

公开(公告)日：2022-11-03

申请号：US17678265

申请日：2022-02-23

Applicant: Intel Corporation

Inventor： Stefan Fechtel ,  Kilian Peter Anton Roth ,  Bertram Gunzelmann ,  Markus Dominik Mueck ,  Ingolf Karls ,  Zhibin Yu ,  Thorsten Clevorn ,  Nageen Himayat ,  Dave A. Cavalcanti ,  Ana Lucia Pinheiro ,  Bahareh Sadeghi ,  Hassnaa Moustafa ,  Marcio Rogerio Juliato ,  Rafael Misoczki ,  Emily H. Qi ,  Jeffrey R. Foerster ,  Duncan Kitchin ,  Debdeep Chatterjee ,  Jong-Kae Fwu ,  Carlos Aldana ,  Shilpa Talwar ,  Harry G. Skinner ,  Debabani Choudhury

IPC: H04W4/40 ,  H04W4/80 ,  H04W8/08 ,  H04W80/02 ,  H04W80/08

Abstract: A communication device for multi-radio access technology (RAT) communications includes one or more processors and a plurality of transceivers. Each transceiver is configured to operate in at least one RAT of a plurality of RATs. The processors are configured to establish connection with a second communication device using a first transceiver of the plurality of transceivers and a first RAT of the plurality of RATs. A first data stream associated with a communication link connected to the second communication device and a third communication device is receive via a convergence function at the second communication device. The communication link uses a second RAT of the plurality of RATs. A code sequence is applied to a second data stream to generate an encoded second data stream, which is transmitted to the third communication device via a second communication link established based on information received via the first data stream.

公开(公告)号：US20220321321A1

公开(公告)日：2022-10-06

申请号：US17833498

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Andrew Reinders ,  Rafael Misoczki ,  Rosario Cammarota ,  Manoj Sastry

IPC: H04L9/00 ,  G06F7/72 ,  G06N3/08 ,  H04L9/06

Abstract: Embodiments are directed to homomorphic encryption for machine learning and neural networks using high-throughput Chinese remainder theorem (CRT) evaluation. An embodiment of an apparatus includes a hardware accelerator to receive a ciphertext generated by homomorphic encryption (HE) for evaluation, decompose coefficients of the ciphertext into a set of decomposed coefficients, multiply the decomposed coefficients using a set of smaller modulus determined based on a larger modulus, and convert results of the multiplying back to an original form corresponding to the larger modulus by performing a reverse Chinese remainder theorem (CRT) transform on the results of multiplying the decomposed coefficients.

公开(公告)号：US20220131706A1

公开(公告)日：2022-04-28

申请号：US17568919

申请日：2022-01-05

Applicant: Intel Corporation

Inventor： Rafael Misoczki ,  Vikram Suresh ,  Santosh Ghosh ,  Manoj Sastry ,  Sanu Mathew ,  Raghavan Kumar

IPC: H04L9/32 ,  H04L9/08

Abstract: In one example an apparatus comprises a computer-readable memory, signature logic to compute a message hash of an input message using a secure hash algorithm, process the message hash to generate an array of secret key components for the input message, apply a hash chain function to the array of secret key components to generate an array of signature components, the hash chain function comprising a series of even-index hash chains and a series of odd-index hash chains, wherein the even-index hash chains and the odd-index hash chains generate a plurality of intermediate node values and a one-time public key component between the secret key components and the signature components and store at least some of the intermediate node values in the computer-readable memory for use in one or more subsequent signature operations. Other examples may be described.

公开(公告)号：US11277406B2

公开(公告)日：2022-03-15

申请号：US16455862

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Xiruo Liu ,  Rafael Misoczki ,  Santosh Ghosh ,  Manoj Sastry

IPC: H04L29/06 ,  H04L9/32 ,  H04L9/08

Abstract: In one example a prover device comprises one or more processors, a computer-readable memory, and signature logic to store a first cryptographic representation of a first trust relationship between the prover device and a verifier device, the first cryptographic representation based on a pair of asymmetric hash-based multi-time signature keys, receive an attestation request message from the verifier device, the attestation request message comprising attestation data for the verifier device and a hash-based signature generated by the verifier device, and in response to the attestation request message, to verify the attestation data, verify the hash-based signature generated by the verifier device using a public key associated with the verifier device, generate an attestation reply message using a hash-based multi-time private signature key and send the attestation reply message to the verifier device. Other examples may be described.

公开(公告)号：US11223483B2

公开(公告)日：2022-01-11

申请号：US16456064

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Rafael Misoczki ,  Vikram Suresh ,  Santosh Ghosh ,  Manoj Sastry ,  Sanu Mathew ,  Raghavan Kumar

IPC: H04L9/32 ,  H04L9/08

Abstract: In one example an apparatus comprises a computer-readable memory, signature logic to compute a message hash of an input message using a secure hash algorithm, process the message hash to generate an array of secret key components for the input message, apply a hash chain function to the array of secret key components to generate an array of signature components, the hash chain function comprising a series of even-index hash chains and a series of odd-index hash chains, wherein the even-index hash chains and the odd-index hash chains generate a plurality of intermediate node values and a one-time public key component between the secret key components and the signature components and store at least some of the intermediate node values in the computer-readable memory for use in one or more subsequent signature operations. Other examples may be described.

公开(公告)号：US10805086B2

公开(公告)日：2020-10-13

申请号：US15848785

申请日：2017-12-20

Applicant: INTEL CORPORATION

Inventor： Mohammed Karmoose ,  Rafael Misoczki ,  Liuyang Yang ,  Xiruo Liu ,  Moreno Ambrosin ,  Manoj R. Sastry

IPC: H04L29/06 ,  H04L9/32 ,  G08G1/00 ,  H04L9/14 ,  H04L9/30 ,  H04L9/06 ,  H04L9/12 ,  H04L29/12

Abstract: Logic may implement protocols and procedures for vehicle-to-vehicle communications for platooning. Logic may implement a communications topology to distinguish time-critical communications from non-time-critical communications. Logic may sign time-critical communications with a message authentication code (MAC) algorithm with a hash function such as Keccak MAC or a Cipher-based MAC. Logic may generate a MAC based on pairwise, symmetric keys to sign the time-critical communications. Logic may sign non-time-critical communications with a digital signature. Logic may encrypt non-time-critical communications. Logic may append a certificate to non-time-critical communications. Logic may append a header to messages to create data packets and may include a packet type to identify time-critical communications. Logic may decode and verify the time-critical messages with a pairwise symmetric key. And logic may prioritize time-critical communications to meet a specified latency.

公开(公告)号：US20200280827A1

公开(公告)日：2020-09-03

申请号：US16623348

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Stefan Fechtel ,  Kilian Roth ,  Bertram Gunzelmann ,  Markus Dominik Mueck ,  Ingolf Karls ,  Zhibin Yu ,  Thorsten Clevorn ,  Nageen Himayat ,  Dave A. Cavalcanti ,  Ana Lucia Pinheiro ,  Bahareh Sadeghi ,  Hassnaa Moustafa ,  Marcio Rogerio Juliato ,  Rafael Misoczki ,  Emily H. Qi ,  Jeffrey R. Foerster ,  Duncan Kitchin ,  Debdeep Chatterjee ,  Jong-Kae Fwu ,  Carlos Aldana ,  Shilpa Talwar ,  Harry G. Skinner ,  Debabani Choudhury

IPC: H04W4/40 ,  H04W80/08 ,  H04W80/02 ,  H04W4/80 ,  H04W8/08

Abstract: Systems, devices, and techniques for V2X communications using multiple radio access technologies (RATs) are described herein. A communication associated with one or more of the multiple RATs may be received at a device. The device may include a transceiver interface with multiple connections to communicate with multiple transceiver chains. The multiple transceiver chains can be configured to support multiple RATs. Additionally, the multiple transceiver chains may be controlled via the multiple connections of the transceiver interface to coordinate the multiple RATs to complete the communication.

公开(公告)号：US10355891B2

公开(公告)日：2019-07-16

申请号：US15720389

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Marcio Juliato ,  Li Zhao ,  Ahmed Shabbir ,  Manoj R. Sastry ,  Santosh Ghosh ,  Rafael Misoczki

IPC: H04L12/40 ,  H04L25/49

Abstract: Embodiments may include systems and methods for authenticating a message between a transmitter and a receiver. An apparatus for communication may include a transmitter to transmit a message to a receiver via a physical channel coupling the transmitter and the receiver. The message may be transmitted via a plurality of transmission voltage levels varied from a plurality of nominal voltage levels on the physical channel. The transmitter may include a voltage generator to generate the plurality of transmission voltage levels varied in accordance with a sequence of voltage variations from the plurality of nominal voltage levels for the message. The sequence of voltage variations may serve to authenticate the message between the transmitter and the receiver. Other embodiments may be described and/or claimed.

公开(公告)号：US10348495B2

公开(公告)日：2019-07-09

申请号：US15441030

申请日：2017-02-23

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Rafael Misoczki ,  Manoj R. Sastry ,  Li Zhao

IPC: H04L9/08 ,  H04L9/32 ,  H04L9/00 ,  H04L9/06

Abstract: Apparatuses and methods associated with configurable crypto hardware engine are disclosed herein. In embodiments, an apparatus for signing or verifying a message may comprise: a hardware hashing computation block to perform hashing computations; a hardware hash chain computation block to perform successive hash chain computations; a hardware private key generator to generate private keys; and a hardware public key generator to generate public keys, including signature generations and signature verifications. The hardware hashing computation block, the hardware hash chain computation block, the hardware private key generator, and the hardware public key generator may be coupled to each other and selectively cooperate with each other to perform private key generation, public key generation, signature generation or signature verification at different points in time. Other embodiments may be disclosed or claimed.