公开(公告)号：US20200058782A1

公开(公告)日：2020-02-20

申请号：US16461353

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/423 ,  H01L29/10

Abstract: A semiconductor device includes a silicon pillar disposed on a substrate, the silicon pillar has a sidewall. A group III-N semiconductor material is disposed on the sidewall of the silicon pillar. The group III-N semiconductor material has a sidewall. A doped source structure and a doped drain structure are disposed on the group III-N semiconductor material. A polarization charge inducing layer is disposed on the sidewall of the group III-N semiconductor material between the doped drain structure and the doped source structure. A plurality of portions of gate dielectric layer is disposed on the sidewalls of the group III-N semiconductor material and between the polarization charge inducing layer. A plurality of resistive gate electrodes separated by an interlayer dielectric layer are disposal adjacent to each of the plurality of portions of the gate dielectric layer. A source metal layer is disposed below and in contact with the doped source structure.

公开(公告)号：US20200006322A1

公开(公告)日：2020-01-02

申请号：US16024705

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Paul FISCHER ,  Walid HAFEZ ,  Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA

IPC: H01L27/06 ,  H01L29/872 ,  H01L21/8252 ,  H01L27/02 ,  H01L29/205 ,  H01L29/20

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed.

公开(公告)号：US20190393211A1

公开(公告)日：2019-12-26

申请号：US16016419

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Paul FISCHER ,  Walid HAFEZ ,  Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA

IPC: H01L27/02 ,  H01L29/10 ,  H01L27/06 ,  H01L21/265

Abstract: A substrate contact diode is disclosed. The substrate contact includes a first type substrate implant tap in a substrate, a second type epitaxial implant in an epitaxial layer that is on the substrate, and a first type epitaxial region above the second type epitaxial implant. A contact electrode that extends upward from the top of the first type epitaxial region to the surface of an interlayer dielectric that surrounds the contact electrode.

公开(公告)号：US20190341899A1

公开(公告)日：2019-11-07

申请号：US16349935

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： Paul FISCHER ,  Mark RADOSAVLJEVIC ,  Sansaptak DASGUPTA ,  Han Wui THEN

IPC: H03H3/02 ,  H03H9/17 ,  H03H9/60

Abstract: Modern RF front end filters feature acoustic resonators in a film bulk acoustic resonator (FBAR) structure. An acoustic filter is a circuit that includes at least (and typically significantly more) two resonators. The acoustic resonator structure comprises a substrate including sidewalls and a vertical cavity between the sidewalls and two or more resonators deposited in the vertical cavity.

公开(公告)号：US20190304896A1

公开(公告)日：2019-10-03

申请号：US16462889

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Sanaz K. GARDNER

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/762 ,  H01L21/764 ,  H01L29/06

Abstract: Embodiments of the invention include a microelectronic device that includes a substrate, at least one dielectric layer on the substrate and a plurality of conductive lines within the at least one dielectric layer. The microelectronic device also includes an air gap structure that is located below two or more of the plurality of conductive lines

公开(公告)号：US20190287935A1

公开(公告)日：2019-09-19

申请号：US16345627

申请日：2016-12-21

Applicant: Intel Corporation

Inventor： Paul B. FISCHER ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA

IPC: H01L23/66 ,  H01L23/14 ,  H01L23/13 ,  H01L23/522 ,  H01L21/50

Abstract: Embodiments of the invention include a microelectronic device that includes an insulating substrate, a RF transistor layer, and an interconnect structure disposed on the RF transistor layer. The RF transistor layer includes RF transistors for microwave frequencies. The interconnect structure includes at least one layer of dielectric material and a conductive layer having a plurality of conductive lines. The insulating substrate reduces parasitic capacitances and parasitic coupling to the insulating substrate.

公开(公告)号：US20190067081A1

公开(公告)日：2019-02-28

申请号：US16083859

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Sanaz K. GARDNER ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Han Wui THEN ,  Seung Hoon SUNG

IPC: H01L21/768 ,  H01L23/31 ,  H01L23/00 ,  H01L29/20 ,  H01L33/20 ,  H01L33/44

Abstract: A method of fabricating a wafer is disclosed. The method includes forming a protective layer on a device side and a non-device side of a substrate of the wafer. The method further includes removing the protective layer from a center portion of the device side of the substrate while retaining the protective layer in an edge portion of the substrate. The method also includes forming semiconductor layer in the center portion of the device side of the substrate while the protective layer is in the edge portion of the substrate.

公开(公告)号：US20180145052A1

公开(公告)日：2018-05-24

申请号：US15574822

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Peter G. TOLCHINSKY ,  Robert S. CHAU

IPC: H01L25/065 ,  H01L27/06 ,  H01L27/092 ,  H01L23/48 ,  H01L29/20 ,  H01L29/778 ,  H01L25/00 ,  H01L21/8252 ,  H01L21/8238 ,  H01L21/02

Abstract: GaN-On-Silicon (GOS) structures and techniques for accommodating and/or controlling stress/strain incurred during III-N growth on a large diameter silicon substrate. A back-side of a silicon substrate may be processed to adapt substrates of standardized diameters and thicknesses to GOS applications. Bowing and/or warping during high temperature epitaxial growth processes may be mitigated by pre-processing silicon substrate so as to pre-stress the substrate in a manner than counterbalances stress induced by the III-N material and/or improve a substrate's ability to absorb stress. III-N devices fabricated on an engineered GOS substrate may be integrated together with silicon MOS devices fabricated on a separate substrate. Structures employed to improve substrate resilience and/or counterbalance the substrate stress induced by the III-N material may be further employed for interconnecting the III-N and silicon MOS devices of a 3D IC.

公开(公告)号：US20170236928A1

公开(公告)日：2017-08-17

申请号：US15499774

申请日：2017-04-27

Applicant: Intel Corporation

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Sanaz K. GARDNER ,  Seung Hoon SUNG ,  Benjamin CHU-KUNG ,  Robert S. CHAU

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/66 ,  H01L21/306 ,  H01L29/20

CPC classification number: H01L29/7783 ,  H01L21/30612 ,  H01L21/30617 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786

Abstract: Transistors or transistor layers include an InAlN and AlGaN bi-layer capping stack on a 2DEG GaN channel, such as for GaN MOS structures on Si substrates. The GaN channel may be formed in a GaN buffer layer or stack, to compensate for the high crystal structure lattice size and coefficient of thermal expansion mismatch between GaN and Si. The bi-layer capping stack an upper InAlN layer on a lower AlGaN layer to induce charge polarization in the channel, compensate for poor composition uniformity (e.g., of Al), and compensate for rough surface morphology of the bottom surface of the InAlN material. It may lead to a sheet resistance between 250 and 350 ohms/sqr. It may also reduce bowing of the GaN on Si wafers during growth of the layer of InAlN material, and provide a AlGaN setback layer for etching the InAlN layer in the gate region.

公开(公告)号：US20170229565A1

公开(公告)日：2017-08-10

申请号：US15329216

申请日：2014-09-09

Applicant: INTEL CORPORATION

Inventor： Kimin JUN ,  Sansaptak DASGUPTA ,  Alejandro X. LEVANDER ,  Patrick MORROW

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/66 ,  H01L29/20

CPC classification number: H01L29/7781 ,  H01L21/76254 ,  H01L29/2003 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/66545

Abstract: A multi-gate high electron mobility transistor (HEMT) and its methods of formation are disclosed. The multi-gate HEMT includes a substrate and an adhesion layer on top of the substrate. A channel layer is disposed on top of the adhesion layer, and a first gate electrode is disposed on top of the channel layer. The first gate electrode has a first gate dielectric layer in between the first gate electrode and the channel layer. A second gate electrode is embedded within the substrate and beneath the channel layer. The second gate electrode has a second gate dielectric layer completely surrounding the second gate electrode. A pair of source and drain contacts are disposed on opposite sides of the first gate electrode.