公开(公告)号：US20240413237A1

公开(公告)日：2024-12-12

申请号：US18808992

申请日：2024-08-19

Applicant: Intel Corporation

Inventor： Patrick MORROW ,  Kimin JUN ,  Il-Seok SON ,  Donald W. NELSON

IPC: H01L29/78 ,  H01L23/00 ,  H01L23/14 ,  H01L23/15 ,  H01L23/31 ,  H01L23/498 ,  H01L29/417

Abstract: An apparatus including a circuit structure including a first side including a device layer including a plurality of devices and an opposite second side; an electrically conductive contact coupled to one of the plurality of devices on the first side; and an electrically conductive interconnect disposed on the second side of the structure and coupled to the conductive contact. A method including forming a transistor device including a channel between a source and a drain and a gate electrode on the channel defining a first side of the device; forming an electrically conductive contact to one of the source and the drain from the first side; and forming an interconnect on a second side of the device, wherein the interconnect is coupled to the contact.

公开(公告)号：US20230066336A1

公开(公告)日：2023-03-02

申请号：US17458112

申请日：2021-08-26

Applicant: Intel Corporation

Inventor： Pratik KOIRALA ,  Paul NORDEEN ,  Tushar TALUKDAR ,  Kimin JUN ,  Thomas HOFF ,  Han Wui THEN ,  Nicole K. THOMAS ,  Marko RADOSAVLJEVIC ,  Paul B. FISCHER

IPC: H01L27/06 ,  H01L29/26 ,  H01L23/48 ,  H01L49/02 ,  H01L29/778 ,  H01L29/04 ,  H01L21/8258 ,  H01L21/822

Abstract: Gallium nitride (GaN) epitaxy on patterned substrates for integrated circuit technology is described. In an example, an integrated circuit structure includes a material layer including gallium and nitrogen, the material layer having a first side and a second side opposite the first side. A plurality of fins is on the first side of the material layer, the plurality of fins including silicon. A device layer is on the second side of the material layer, the device layer including one or more GaN-based devices.

公开(公告)号：US20230054719A1

公开(公告)日：2023-02-23

申请号：US17408025

申请日：2021-08-20

Applicant: Intel Corporation

Inventor： Pratik KOIRALA ,  Souvik GHOSH ,  Paul NORDEEN ,  Tushar TALUKDAR ,  Thomas HOFF ,  Ibrahim BAN ,  Kimin JUN ,  Samuel James BADER ,  Marko RADOSAVLJEVIC ,  Nicole K. THOMAS ,  Paul B. FISCHER ,  Han Wui THEN

IPC: H01L29/778 ,  H01L29/20

Abstract: Gallium nitride (GaN) layer transfer and regrowth for integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate. An insulator layer is over the substrate. A device layer is directly on the insulator layer. The device layer has a thickness of less than approximately 500 nanometers.

公开(公告)号：US20220130803A1

公开(公告)日：2022-04-28

申请号：US17572219

申请日：2022-01-10

Applicant: Intel Corporation

Inventor： Brennen K. MUELLER ,  Patrick MORROW ,  Kimin JUN ,  Paul B. FISCHER ,  Daniel PANTUSO

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/768 ,  H01L21/762 ,  H01L21/84 ,  H01L23/485 ,  H01L21/48 ,  H01L23/48 ,  H01L23/498 ,  H01L27/12

Abstract: An apparatus including a circuit structure including a device stratum; one or more electrically conductive interconnect levels on a first side of the device stratum and coupled to ones of the transistor devices; and a substrate including an electrically conductive through silicon via coupled to the one or more electrically conductive interconnect levels so that the one or more interconnect levels are between the through silicon via and the device stratum. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum; forming one or more interconnect levels on a first side of the device stratum; removing a portion of the substrate; and coupling a through silicon via to the one or more interconnect levels such that the one or more interconnect levels is disposed between the device stratum and the through silicon via.

公开(公告)号：US20200212038A1

公开(公告)日：2020-07-02

申请号：US16236113

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Aaron LILAK ,  Brennen MUELLER ,  Hui Jae YOO ,  Patrick MORROW ,  Anh PHAN ,  Cheng-Ying HUANG ,  Ehren MANNEBACH ,  Kimin JUN ,  Gilbert DEWEY

IPC: H01L27/092 ,  H01L29/16 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8238

Abstract: An integrated circuit structure comprises a substrate and a stacked channel of self-aligned heterogeneous materials, wherein the stacked channel of self-aligned heterogeneous materials comprises an NMOS channel material over the substrate; and a PMOS channel material stacked over and self-aligned with the NMOS channel material. A heterogeneous gate stack is in contact the both the NMOS channel material and the PMOS channel material.

公开(公告)号：US20180323174A1

公开(公告)日：2018-11-08

申请号：US15773514

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Brennen K. MUELLER ,  Patrick MORROW ,  Kimin JUN ,  Paul B. FISCHER ,  Daniel PANTUSO

IPC: H01L25/065 ,  H01L27/12 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L21/76251 ,  H01L21/76838 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L27/1203 ,  H01L27/1211 ,  H01L2224/02331 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/06181 ,  H01L2224/06182 ,  H01L2224/08146 ,  H01L2224/08235 ,  H01L2224/09181 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16141 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/48105 ,  H01L2224/48228 ,  H01L2224/48464 ,  H01L2224/73257 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/014

Abstract: An apparatus including a circuit structure including a device stratum; one or more electrically conductive interconnect levels on a first side of the device stratum and coupled to ones of the transistor devices; and a substrate including an electrically conductive through silicon via coupled to the one or more electrically conductive interconnect levels so that the one or more inter connect levels are between the through silicon via and the device stratum. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum; forming one or more interconnect levels on a first side of the device stratum; removing a portion of the substrate; and coupling a through silicon via to the one or more interconnect levels such that the one or more interconnect levels is disposed between the device stratum and the through silicon via.

公开(公告)号：US20170011929A1

公开(公告)日：2017-01-12

申请号：US15120720

申请日：2014-09-24

Applicant: INTEL CORPORATION

Inventor： Kimin JUN ,  Patrick MORROW ,  Donald NELSON

IPC: H01L21/308 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/3086 ,  H01L21/3081 ,  H01L21/76802 ,  H01L29/0676 ,  H01L29/66666 ,  H01L29/7827

Abstract: A grid comprising a first set of grid lines and a second set of grid lines is formed on a substrate using a first lithography process. At least one of the first set of grid lines and the second set of grid lines are selectively patterned to define a vertical device feature using a second lithography process.

Abstract translation: 使用第一光刻工艺在衬底上形成包括第一组栅格线和第二组栅格线的栅格。 第一组栅格线和第二组栅格线中的至少一个被选择性地图案化以使用第二光刻工艺限定垂直器件特征。

公开(公告)号：US20250070083A1

公开(公告)日：2025-02-27

申请号：US18942054

申请日：2024-11-08

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Henning BRAUNISCH ,  Aleksandar ALEKSOV ,  Shawna M. LIFF ,  Johanna M. SWAN ,  Patrick MORROW ,  Kimin JUN ,  Brennen MUELLER ,  Paul B. FISCHER

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.

公开(公告)号：US20240194533A1

公开(公告)日：2024-06-13

申请号：US18389625

申请日：2023-12-19

Applicant: Intel Corporation

Inventor： Valluri R. RAO ,  Patrick MORROW ,  Rishabh MEHANDRU ,  Doug INGERLY ,  Kimin JUN ,  Kevin O'BRIEN ,  Paul FISCHER ,  Szuya S. LIAO ,  Bruce BLOCK

IPC: H01L21/822 ,  G01R1/073 ,  H01L21/306 ,  H01L21/66 ,  H01L21/683 ,  H01L21/8238 ,  H01L23/00 ,  H01L23/528 ,  H01L23/532 ,  H01L25/065 ,  H01L27/092 ,  H01L27/12 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L21/8221 ,  H01L21/30625 ,  H01L21/6835 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L22/14 ,  H01L23/528 ,  H01L23/53233 ,  H01L24/03 ,  H01L24/05 ,  H01L27/0924 ,  H01L27/1207 ,  H01L29/04 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/20 ,  G01R1/07307 ,  H01L24/08 ,  H01L25/0657 ,  H01L27/1214 ,  H01L27/1222 ,  H01L29/66545 ,  H01L2221/68345 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/08147 ,  H01L2225/06565

Abstract: Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Electrical test may be performed from front and back sides of a workpiece. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.

公开(公告)号：US20210175124A1

公开(公告)日：2021-06-10

申请号：US17112697

申请日：2020-12-04

Applicant: Intel Corporation

Inventor： Valluri R. RAO ,  Patrick MORROW ,  Rishabh MEHANDRU ,  Doug INGERLY ,  Kimin JUN ,  Kevin O'BRIEN ,  Paul FISCHER ,  Szuya S. LIAO ,  Bruce BLOCK

IPC: H01L21/822 ,  H01L21/8238 ,  H01L27/12 ,  H01L21/683 ,  H01L23/00 ,  H01L27/092 ,  H01L21/306 ,  H01L29/04 ,  H01L23/528 ,  H01L29/08 ,  H01L21/66 ,  H01L29/06 ,  H01L29/20 ,  H01L23/532 ,  H01L29/16 ,  G01R1/073 ,  H01L29/66 ,  H01L25/065

Abstract: Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Electrical test may be performed from front and back sides of a workpiece. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.