公开(公告)号：US20190278022A1

公开(公告)日：2019-09-12

申请号：US16462077

申请日：2016-12-30

申请人： Intel Corporation

发明人： Rahul RAMASWAMY ,  Chia-Hong JAN ,  Walid HAFEZ ,  Neville DIAS ,  Hsu-Yu CHANG ,  Roman W. OLAC-VAW ,  Chen-Guan LEE

IPC分类号： G02B6/122 ,  G02B6/12 ,  G02B6/134 ,  G02B6/136

摘要： Embodiments of the invention include an electromagnetic waveguide and methods of forming electromagnetic waveguides. In an embodiment, the electromagnetic waveguide may include a first semiconductor fin extending up from a substrate and a second semiconductor fin extending up from the substrate. The fins may be bent towards each other so that a centerline of the first semiconductor fin and a centerline of the second semiconductor fin extend from the substrate at a non-orthogonal angle. Accordingly, a cavity may be defined by the first semiconductor fin, the second semiconductor fin, and a top surface of the substrate. Embodiments of the invention may include a metallic layer and a cladding layer lining the surfaces of the cavity. Additional embodiments may include a core formed in the cavity.

公开(公告)号：US20190356032A1

公开(公告)日：2019-11-21

申请号：US16461554

申请日：2016-12-30

申请人： Intel Corporation

发明人： Rahul RAMASWAMY ,  Chia-Hong JAN ,  Walid HAFEZ ,  Neville DIAS ,  Hsu-Yu CHANG ,  Roman OLAC-VAW ,  Chen-Guan LEE

IPC分类号： H01P3/12 ,  H01P5/12 ,  H01P11/00 ,  H01L21/768 ,  H01L23/66 ,  H01L21/8234 ,  H01P3/127

摘要： Embodiments of the invention include an electromagnetic waveguide and methods of forming the electromagnetic waveguide. In an embodiment the electromagnetic waveguide includes a first spacer and a second spacer. In an embodiment, the first and second spacer each have a reentrant profile. The electromagnetic waveguide may also include a conductive body formed between in the first and second spacer, and a void formed within the conductive body. In an additional embodiment, the electromagnetic waveguide may include a first spacer and a second spacer. Additionally, the electromagnetic waveguide may include a first portion of a conductive body formed along sidewalls of the first and second spacer and a second portion of the conductive body formed between an upper portion of the first portion of the conductive body. In an embodiment, the first portion of the conductive body and the second portion of the conductive body define a void through the electromagnetic waveguide.

公开(公告)号：US20170162503A1

公开(公告)日：2017-06-08

申请号：US15327338

申请日：2014-08-19

申请人： INTEL CORPORATION

发明人： Roman OLAC-VAW ,  Walid HAFEZ ,  Chia-Hong JAN ,  Hsu-Yu CHANG ,  Ting CHANG ,  Rahul RAMASWAMY ,  Pei-Chi LIU ,  Neville DIAS

IPC分类号： H01L23/525 ,  H01L29/78 ,  H01L29/423 ,  H01L21/768

摘要： A MOS antifuse with an accelerated dielectric breakdown induced by a void or seam formed in the electrode. In some embodiments, the programming voltage at which a MOS antifuse undergoes dielectric breakdown is reduced through intentional damage to at least part of the MOS antifuse dielectric. In some embodiments, damage may be introduced during an etchback of an electrode material which has a seam formed during backfilling of the electrode material into an opening having a threshold aspect ratio. In further embodiments, a MOS antifuse bit-cell includes a MOS transistor and a MOS antifuse. The MOS transistor has a gate electrode that maintains a predetermined voltage threshold swing, while the MOS antifuse has a gate electrode with a void accelerated dielectric breakdown.

公开(公告)号：US20200006322A1

公开(公告)日：2020-01-02

申请号：US16024705

申请日：2018-06-29

申请人： Intel Corporation

发明人： Han Wui THEN ,  Paul FISCHER ,  Walid HAFEZ ,  Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA

IPC分类号： H01L27/06 ,  H01L29/872 ,  H01L21/8252 ,  H01L27/02 ,  H01L29/205 ,  H01L29/20

摘要： Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed.

公开(公告)号：US20190393211A1

公开(公告)日：2019-12-26

申请号：US16016419

申请日：2018-06-22

申请人： Intel Corporation

发明人： Han Wui THEN ,  Paul FISCHER ,  Walid HAFEZ ,  Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA

IPC分类号： H01L27/02 ,  H01L29/10 ,  H01L27/06 ,  H01L21/265

摘要： A substrate contact diode is disclosed. The substrate contact includes a first type substrate implant tap in a substrate, a second type epitaxial implant in an epitaxial layer that is on the substrate, and a first type epitaxial region above the second type epitaxial implant. A contact electrode that extends upward from the top of the first type epitaxial region to the surface of an interlayer dielectric that surrounds the contact electrode.

公开(公告)号：US20230299081A1

公开(公告)日：2023-09-21

申请号：US17695738

申请日：2022-03-15

申请人： Intel Corporation

发明人： Leonard P. GULER ,  Sairam SUBRAMANIAN ,  Walid HAFEZ ,  Charles H. WALLACE

IPC分类号： H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/775 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/66

CPC分类号： H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/02603 ,  H01L21/28123 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/66439

摘要： Gate-all-around integrated circuit structures having pre-spacer-deposition wide cut gates with extensions are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. A first dielectric gate spacer is along an end of the first gate stack in the gap. A second dielectric gate spacer is along an end of the second gate stack in the gap. A dielectric material is between and in lateral contact with the first dielectric gate spacer and the second dielectric gate spacer.

公开(公告)号：US20190393311A1

公开(公告)日：2019-12-26

申请号：US16016406

申请日：2018-06-22

申请人： Intel Corporation

发明人： Marko RADOSAVLJEVIC ,  Han Wui THEN ,  Sansaptak DASGUPTA ,  Paul FISCHER ,  Walid HAFEZ

IPC分类号： H01L29/15 ,  H01L29/423 ,  H01L29/08 ,  H01L27/088 ,  H01L21/02 ,  H01L21/8252 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/66 ,  H01L21/306

摘要： A semiconductor device is disclosed. The semiconductor device includes a substrate, a superlattice that includes a plurality of layers of alternating materials above the substrate, where each of the plurality of layers corresponds to a threshold voltage, a gate trench extending into the superlattice to a predetermined one of the plurality of layers of the superlattice structure, and a high-k layer on the bottom and sidewall of the trench, the high-k layer contacting an etch stop layer of one of the plurality of layers of alternating materials. A gate is located in the trench on top of the high-k layer.

公开(公告)号：US20190393332A1

公开(公告)日：2019-12-26

申请号：US16016411

申请日：2018-06-22

申请人： Intel Corporation

发明人： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA ,  Paul FISCHER ,  Walid HAFEZ

IPC分类号： H01L29/778 ,  H01L29/08 ,  H01L29/20 ,  H01L29/205 ,  H01L21/02 ,  H01L29/66

摘要： A semiconductor device is disclosed. The semiconductor device includes a substrate, an epitaxial layer on the substrate, a semiconductor interlayer on top of the epitaxial layer, a gate conductor above the semiconductor interlayer, a gate insulator on the bottom and sides of the gate conductor and contacting the top surface of the semiconductor interlayer, a source region extending into the epitaxial layer, and a drain region extending into the epitaxial layer. The semiconductor device also includes a first polarization layer on the semiconductor interlayer between the source region and the gate conductor and a second polarization layer on the semiconductor interlayer between the drain region and the gate conductor.

公开(公告)号：US20190393210A1

公开(公告)日：2019-12-26

申请号：US16016396

申请日：2018-06-22

申请人： Intel Corporation

发明人： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Paul FISCHER ,  Walid HAFEZ

IPC分类号： H01L27/02 ,  H01L29/20 ,  H01L29/06 ,  H01L29/872 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L21/265

摘要： A semiconductor device is disclosed. The semiconductor device includes a substrate, an epitaxial layer above the substrate, a Schottky barrier material on the epitaxial layer, a Schottky metal contact extending into the Schottky barrier material, a fin structure that extends in a first direction, a first angled implant in a first side of the fin structure that has an orientation that is orthogonal to the first direction, and a second angled implant in a second side of the fin structure that has an orientation that is orthogonal to the first direction. The second side is opposite to the first side. A first cathode region and a second cathode region are coupled by parts of the first angled implant and the second angled implant that extend in the first direction.

公开(公告)号：US20190393041A1

公开(公告)日：2019-12-26

申请号：US16013860

申请日：2018-06-20

申请人： Intel Corporation

发明人： Marko RADOSAVLJEVIC ,  Han Wui THEN ,  Sansaptak DASGUPTA ,  Paul FISCHER ,  Walid HAFEZ

IPC分类号： H01L21/28 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L29/778 ,  H01L29/66

摘要： A transistor gate is disclosed. The transistor gate includes a first part above a substrate that has a first width and a second part above the first part that is centered with respect to the first part and that has a second width that is greater than the first width. The first part and the second part form a single monolithic T-gate structure.