公开(公告)号：US20240413237A1

公开(公告)日：2024-12-12

申请号：US18808992

申请日：2024-08-19

Applicant: Intel Corporation

Inventor： Patrick MORROW ,  Kimin JUN ,  Il-Seok SON ,  Donald W. NELSON

IPC: H01L29/78 ,  H01L23/00 ,  H01L23/14 ,  H01L23/15 ,  H01L23/31 ,  H01L23/498 ,  H01L29/417

Abstract: An apparatus including a circuit structure including a first side including a device layer including a plurality of devices and an opposite second side; an electrically conductive contact coupled to one of the plurality of devices on the first side; and an electrically conductive interconnect disposed on the second side of the structure and coupled to the conductive contact. A method including forming a transistor device including a channel between a source and a drain and a gate electrode on the channel defining a first side of the device; forming an electrically conductive contact to one of the source and the drain from the first side; and forming an interconnect on a second side of the device, wherein the interconnect is coupled to the contact.

公开(公告)号：US20240332403A1

公开(公告)日：2024-10-03

申请号：US18738693

申请日：2024-06-10

Applicant: Intel Corporation

Inventor： Patrick MORROW ,  Rishabh MEHANDRU ,  Aaron D. LILAK

IPC: H01L29/66 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66795 ,  H01L21/8221 ,  H01L21/823842 ,  H01L21/823871 ,  H01L27/0688 ,  H01L27/092 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/78696 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0673

Abstract: A first interconnect layer is bonded to a first substrate. The first interconnect layer is deposited on a first device layer on a second device layer on a second substrate. The second device layer is revealed from the second substrate side. A first insulating layer is deposited on the revealed second device layer. A first opening is formed in the first insulating layer to expose a first portion of the second device layer. A contact region is formed on the exposed first portion of the second device layer.

公开(公告)号：US20230377947A1

公开(公告)日：2023-11-23

申请号：US18356780

申请日：2023-07-21

Applicant: Intel Corporation

Inventor： Cheng-Ying HUANG ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Aaron LILAK ,  Ehren MANNEBACH ,  Patrick MORROW ,  Anh PHAN ,  Willy RACHMADY ,  Hui Jae YOO

IPC: H01L21/762 ,  H01L21/225 ,  H01L21/265 ,  H01L21/02 ,  H01L29/78 ,  H01L29/06 ,  H01L21/311 ,  H01L21/266

CPC classification number: H01L21/76264 ,  H01L21/2253 ,  H01L21/2255 ,  H01L21/26533 ,  H01L21/02236 ,  H01L21/02252 ,  H01L29/7853 ,  H01L29/0649 ,  H01L21/31111 ,  H01L21/76267 ,  H01L21/02255 ,  H01L21/266

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes to form volumes of oxide within a fin, such as a Si fin. In embodiments, this may be accomplished by applying a catalytic oxidant material on a side of a fin and then annealing to form a volume of oxide. In embodiments, this may be accomplished by using a plasma implant technique or a beam-line implant technique to introduce oxygen ions into an area of the fin and then annealing to form a volume of oxide. Processes described here may be used manufacture a transistor, a stacked transistor, or a three-dimensional (3-D) monolithic stacked transistor.

公开(公告)号：US20220130803A1

公开(公告)日：2022-04-28

申请号：US17572219

申请日：2022-01-10

Applicant: Intel Corporation

Inventor： Brennen K. MUELLER ,  Patrick MORROW ,  Kimin JUN ,  Paul B. FISCHER ,  Daniel PANTUSO

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/768 ,  H01L21/762 ,  H01L21/84 ,  H01L23/485 ,  H01L21/48 ,  H01L23/48 ,  H01L23/498 ,  H01L27/12

Abstract: An apparatus including a circuit structure including a device stratum; one or more electrically conductive interconnect levels on a first side of the device stratum and coupled to ones of the transistor devices; and a substrate including an electrically conductive through silicon via coupled to the one or more electrically conductive interconnect levels so that the one or more interconnect levels are between the through silicon via and the device stratum. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum; forming one or more interconnect levels on a first side of the device stratum; removing a portion of the substrate; and coupling a through silicon via to the one or more interconnect levels such that the one or more interconnect levels is disposed between the device stratum and the through silicon via.

公开(公告)号：US20220123128A1

公开(公告)日：2022-04-21

申请号：US17567753

申请日：2022-01-03

Applicant: Intel Corporation

Inventor： Patrick MORROW ,  Rishabh MEHANDRU ,  Aaron D. LILAK

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092

Abstract: A first interconnect layer is bonded to a first substrate. The first interconnect layer is deposited on a first device layer on a second device layer on a second substrate. The second device layer is revealed from the second substrate side . A first insulating layer is deposited on the revealed second device layer. A first opening is formed in the first insulating layer to expose a first portion of the second device layer. A contact region is formed on the exposed first portion of the second device layer.

公开(公告)号：US20200273779A1

公开(公告)日：2020-08-27

申请号：US16646129

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Anh PHAN ,  Patrick MORROW ,  Stephanie A. BOJARSKI

IPC: H01L23/48 ,  H01L27/088 ,  H01L21/8234

Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a first set of transistor fins and a first set of contact metallization. An upper device layer is bonded onto the lower device layer, where the upper device layer includes a second structure comprising a second set of transistor fins and a second set of contact metallization. At least one power isolation wall extends from a top of the upper device layer to the bottom of the lower device layer, wherein the power isolation wall is filled with a conductive material such that power is routed between transistor devices on the upper device layer and the lower device layer.

公开(公告)号：US20200212038A1

公开(公告)日：2020-07-02

申请号：US16236113

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Aaron LILAK ,  Brennen MUELLER ,  Hui Jae YOO ,  Patrick MORROW ,  Anh PHAN ,  Cheng-Ying HUANG ,  Ehren MANNEBACH ,  Kimin JUN ,  Gilbert DEWEY

IPC: H01L27/092 ,  H01L29/16 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8238

Abstract: An integrated circuit structure comprises a substrate and a stacked channel of self-aligned heterogeneous materials, wherein the stacked channel of self-aligned heterogeneous materials comprises an NMOS channel material over the substrate; and a PMOS channel material stacked over and self-aligned with the NMOS channel material. A heterogeneous gate stack is in contact the both the NMOS channel material and the PMOS channel material.

公开(公告)号：US20190221577A1

公开(公告)日：2019-07-18

申请号：US16324479

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Patrick THEOFANIS ,  Patrick MORROW ,  Rishabh MEHANDRU ,  Stephen M. CEA

IPC: H01L27/11582 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L27/11575

Abstract: An apparatus including an array of at least two vertically stacked layers of integrated circuit device components separated by a dielectric layer on a substrate, wherein each of the at least two vertically stacked layers includes a laterally disposed contact point; and an electrically conductive interconnection coupled to a lateral edge of the contact point of each of the at least two vertically stacked layers and bridging the dielectric layer. A method including forming an array of at least two vertically stacked layers of integrated circuit device components separated by a dielectric layer on a substrate, forming a trench that exposes a lateral contact point of each of the at least two vertically stacked layers; depositing a polymer in the trench, wherein the polymer preferentially aligns to a material of the lateral contact point and bridges the dielectric layer; and modifying or replacing the polyconductive material.

公开(公告)号：US20190027503A1

公开(公告)日：2019-01-24

申请号：US15752241

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Patrick MORROW ,  Stephen M. CEA ,  Rishabh MEHANDRU ,  Cory E. WEBER

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/265 ,  H01L21/3115

Abstract: Embodiments of the present invention are directed to formation of fins with different active channel heights in a tri-gate or a Fin-FET device. In an embodiment, at least two fins are formed on a front side of the substrate. A gate structure extends over a top surface and a pair of sidewalls of at least a portion of the fins. In an embodiment, the substrate is thinned to expose the bottom surface of the fins. Next, backside etching may be performed on each fin to form active channel regions. The fins may be recessed to different depths, forming active channel regions with differing heights.

公开(公告)号：US20180323174A1

公开(公告)日：2018-11-08

申请号：US15773514

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Brennen K. MUELLER ,  Patrick MORROW ,  Kimin JUN ,  Paul B. FISCHER ,  Daniel PANTUSO

IPC: H01L25/065 ,  H01L27/12 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L21/76251 ,  H01L21/76838 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L27/1203 ,  H01L27/1211 ,  H01L2224/02331 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/06181 ,  H01L2224/06182 ,  H01L2224/08146 ,  H01L2224/08235 ,  H01L2224/09181 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16141 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/48105 ,  H01L2224/48228 ,  H01L2224/48464 ,  H01L2224/73257 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/014

Abstract: An apparatus including a circuit structure including a device stratum; one or more electrically conductive interconnect levels on a first side of the device stratum and coupled to ones of the transistor devices; and a substrate including an electrically conductive through silicon via coupled to the one or more electrically conductive interconnect levels so that the one or more inter connect levels are between the through silicon via and the device stratum. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum; forming one or more interconnect levels on a first side of the device stratum; removing a portion of the substrate; and coupling a through silicon via to the one or more interconnect levels such that the one or more interconnect levels is disposed between the device stratum and the through silicon via.