公开(公告)号：US11095427B1

公开(公告)日：2021-08-17

申请号：US17033059

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Rotem Banin ,  Elan Banin ,  Ofir Degani ,  Ronen Gernizky ,  Ashoke Ravi

IPC: H04L7/033 ,  H04B1/403

Abstract: A transceiver, including a modulation circuit configured to modulate a first digital word into a first modulated time signal; and a demodulation circuit configured to demodulate a second modulated time signal into a second digital word, wherein the modulation and demodulation circuits are operable without an external clock source, and inseparably share one or more same circuit elements. Also, a tunable delay line may be configured to set a time rate of the modulation, wherein the modulation circuit and the demodulation circuit inseparably share the tunable delay line.

公开(公告)号：US20200228122A1

公开(公告)日：2020-07-16

申请号：US16629170

申请日：2017-08-07

Applicant: Intel Corporation

Inventor： Ashoke Ravi ,  Ofir Degani

IPC: H03L7/081 ,  H03L7/099 ,  H04L25/03

Abstract: Aspects of present disclosure of multiplying delay lock loop (MDLL) circuitry and communication devices are generally described herein. The MDLL circuitry may comprise a multiplexer and a ring oscillator. The ring oscillator may comprise a cascade of delay elements. The multiplexer may receive a reference clock signal and may receive a ring oscillator output signal from a final delay element of the cascade of delay elements. The multiplexer may select, as a ring oscillator input signal, either the reference clock signal or the ring oscillator output signal. The ring oscillator may determine a jitter estimate based at least partly on a comparison between output signals of two particular delay elements of the cascade. The ring oscillator may compensate delay responses of the delay elements of the cascade based at least partly on the jitter estimate.

公开(公告)号：US20200028722A1

公开(公告)日：2020-01-23

申请号：US16586418

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Kailash Chandrashekar ,  Ashoke Ravi

IPC: H04L27/10 ,  H04L27/152 ,  H03M1/68 ,  H03M1/82

Abstract: Methods, apparatus, systems and articles of manufacture for wideband and fast chirp generation for radar systems are disclosed herein. An example apparatus includes a phase digital-to-analog converter to convert a digital input that specifies at least one of a phase modulation or a frequency modulation into an analog output, and to generate a phase modulated output centered on an intermediate frequency. The example apparatus also includes a frequency multiplier to frequency multiply the phase modulated output centered on the intermediate frequency by a multiplication factor to generate a chirp signal.

公开(公告)号：US10111173B2

公开(公告)日：2018-10-23

申请号：US15164667

申请日：2016-05-25

Applicant: INTEL CORPORATION

Inventor： Erkan Alpman ,  Ahmad B. Khairi ,  Stefano Pellerano ,  Ashoke Ravi

IPC: H04B1/16 ,  H04W52/02

Abstract: An apparatus is provided which comprises: a mixer to mix a first signal of a first frequency with a second signal of a second frequency, and to generate a first output; a switched-capacitor multiplier, coupled to the mixer, to receive the first output and to provide a second output with reduced noise; and an amplifier, coupled to the switched-capacitor multiplier, to amplify the second output.

公开(公告)号：US20150381337A1

公开(公告)日：2015-12-31

申请号：US14318799

申请日：2014-06-30

Applicant: Intel Corporation

Inventor： Paolo Madoglio ,  Georgios Palaskas ,  Stefano Pellerano ,  Ashoke Ravi ,  Kailash Chandrashekar

IPC: H04L7/00 ,  H04B17/21

CPC classification number: H04L7/0004 ,  G04F10/005 ,  H04B17/14 ,  H04B17/21 ,  H04L7/0087

Abstract: This application discusses, among other things, calibration systems for ameliorating nonlinearity of a digital-to-time converter (DTC). In an example, a calibration system can include a calibration path configured to represent a segment of the DTC, a time-to-digital circuit configured to receive an output of the calibration path and the processed frequency information and to provide timing error information of the segment, and a calibration engine configured to receive controller modulation information from a main controller, to provide calibration modulation information to the DTC, to receive the timing error information, and to provide compensation information to a correction circuit coupled to the DTC using the timing error information.

Abstract translation: 该应用程序除其他外还讨论了用于改善数字 - 时间转换器（DTC）的非线性的校准系统。 在一个示例中，校准系统可以包括被配置为表示DTC的段的校准路径，配置成接收校准路径的输出和经处理的频率信息的时间到数字电路，并且提供定时误差信息 并且校准引擎被配置为从主控制器接收控制器调制信息，以向DTC提供校准调制信息以接收定时误差信息，并且使用定时误差向耦合到DTC的校正电路提供补偿信息 信息。

公开(公告)号：US09137084B2

公开(公告)日：2015-09-15

申请号：US13958295

申请日：2013-08-02

Applicant: Intel Corporation

Inventor： Ofir Degani ,  Rotem Banin ,  Ashoke Ravi

IPC: H04L27/36 ,  H03F1/02 ,  H03F3/217 ,  H03F3/24

CPC classification number: H04L27/36 ,  H03F1/0216 ,  H03F3/2175 ,  H03F3/245

Abstract: A Digital-to-Time (DTC) for a Digital Polar Transmitter (DPT) comprises a coarse delay/phase segment and a fine delay/phase segment. The coarse delay/phase segment generates an even delay/phase signal and an odd delay/phase signal. The fine/phase delay segment receives the even coarse phase signal and the odd coarse phase signal, and is responsive to a fine delay/phase control signal to generate a fine delay/phase output signal that is an interpolation of the even delay/phase signal and the odd delay/phase signal. In one exemplary embodiment, the fine delay/phase control signal comprises a binary signal having 2N values, and the fine delay/phase segment comprises 2N interpolators. Each interpolator is coupled to the even and odd coarse phase signals and is controlled by the fine delay/phase control signal to be responsive to the even coarse phase signal or the odd coarse phase signal based on a value of the fine delay/phase control signal.

Abstract translation: 用于数字极性发射器（DPT）的数字时间（DTC）包括粗延迟/相位段和精细延迟/相位段。 粗延迟/相位段产生均匀的延迟/相位信号和奇数延迟/相位信号。 精细/相位延迟段接收均匀粗略相位信号和奇数粗略相位信号，并且响应于精细延迟/相位控制信号以产生精细延迟/相位输出信号，其是偶数延迟/相位信号的内插 和奇延迟/相位信号。 在一个示例性实施例中，精细延迟/相位控制信号包括具有2N个值的二进制信号，并且精细延迟/相位段包括2N个内插器。 每个内插器耦合到偶数和奇数粗略相位信号，并由细微延迟/相位控制信号控制，以响应于均匀粗略相位信号或奇数粗略相位信号，基于精细延迟/相位控制信号的值 。