公开(公告)号：US10331582B2

公开(公告)日：2019-06-25

申请号：US15430765

申请日：2017-02-13

申请人： INTEL CORPORATION

发明人： Ishwar S. Bhati ,  Huichu Liu ,  Jayesh Gaur ,  Kunal Korgaonkar ,  Sasikanth Manipatruni ,  Sreenivas Subramoney ,  Tanay Karnik ,  Hong Wang ,  Ian A. Young

IPC分类号： G06F13/16 ,  G06F12/0811

摘要： A processor includes a processing core and a cache controller including a read queue and a separate write queue. The read queue is to buffer read requests of the processing core to a non-volatile memory, last level cache (NVM-LLC), and the write queue is to buffer write requests to the NVM-LLC. The cache controller is to detect whether the write queue is full. The cache controller further prioritizes a first order of sending requests to the NVM-LLC when the write queue contains an empty slot, the first order specifying a first pattern of sending the read requests before the write requests, and prioritizes a second order of sending requests to the NVM-LLC in response to a determination that the write queue is full, the second order specifying a second pattern of alternating between sending a write request from the write queue and a read request from the read queue.

公开(公告)号：US20190079877A1

公开(公告)日：2019-03-14

申请号：US15701795

申请日：2017-09-12

申请人： Intel Corporation

发明人： Jayesh Gaur ,  Sreenivas Subramoney ,  Sanjay Ganapathy

IPC分类号： G06F12/126 ,  G06F12/0862 ,  G06F12/0811 ,  G06F12/128

摘要： In one embodiment, a processor includes: a first cache controller to control a first cache memory. This cache controller may include a replacement circuit to: associate a first priority indicator with a first cache line based on storage of demand data in the first cache line and first learning information associated with a set of demand-based categories of cache lines; and associate a second priority indicator with a second cache line based on storage of prefetch data in the second cache line and second learning information associated with a set of prefetch-based categories of cache lines. Other embodiments are described and claimed.

公开(公告)号：US10176099B2

公开(公告)日：2019-01-08

申请号：US15206589

申请日：2016-07-11

申请人： Intel Corporation

发明人： Jayesh Gaur ,  Supratik Majumder ,  Zvika Greenfield ,  Israel Diamand

IPC分类号： G06F12/0864 ,  G06F12/08 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0831 ,  G06F15/78 ,  G11C11/406 ,  G06F12/0897

摘要： An apparatus includes a cache controller, the cache controller to receive, from a requestor, a memory access request referencing a memory address of a memory. The cache controller may identify a cache entry associated with the memory address, and responsive to determining that a first data item stored in the cache entry matches a data pattern indicating cache entry invalidity, read a second data item from a memory location identified by the memory address. The cache controller may then return, to the requestor, a response comprising the second data item.