公开(公告)号：US10749104B2

公开(公告)日：2020-08-18

申请号：US16217807

申请日：2018-12-12

Applicant: Intel Corporation

Inventor： Huichu Liu ,  Daniel Morris ,  Tanay Karnik ,  Sasikanth Manipatruni ,  Kaushik Vaidyanathan ,  Ian Young

IPC: H01L43/02 ,  H03K19/18 ,  H01L27/22 ,  H01L43/10

Abstract: Some embodiments include apparatuses having a first magnet, a first stack of layers coupled to a first portion of the first magnet, a first layer coupled to a second portion of the first magnet, a second magnet, a second stack of layers coupled to a first portion of the second magnet, a second layer coupled to a second portion of the second magnet, a conductor coupled to the first stack of layers and to the second layer, and a conductive path coupled to the first portion of the first magnet and to the first portion of the second magnet, each of the first and second layers including a magnetoelectric material, each of the first and second stacks of layers providing an inverse spin orbit coupling effect.

公开(公告)号：US20180285268A1

公开(公告)日：2018-10-04

申请号：US15475197

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Kunal Kishore Korgaonkar ,  Ishwar S. Bhati ,  Huichu Liu ,  Jayesh Gaur ,  Sasikanth Manipatruni ,  Sreenivas Subramoney ,  Tanay Karnik ,  Hong Wang ,  Ian A. Young

IPC: G06F12/0811 ,  G06F12/0808 ,  G06F12/1045 ,  G06F13/40

Abstract: In one embodiment, a processor comprises a processing core, a last level cache (LLC), and a mid-level cache. The mid-level cache is to determine that an idle indicator has been set, wherein the idle indicator is set based on an amount of activity at the LLC, and based on the determination that the idle indicator has been set, identify a first cache line to be evicted from a first set of cache lines of the mid-level cache and send a request to write the first cache line to the LLC.

公开(公告)号：US20180232311A1

公开(公告)日：2018-08-16

申请号：US15430765

申请日：2017-02-13

Applicant: INTEL CORPORATION

Inventor： Ishwar S. Bhati ,  Huichu Liu ,  Jayesh Gaur ,  Kunal Korgaonkar ,  Sasikanth Manipatruni ,  Sreenivas Subramoney ,  Tanay Karnik ,  Hong Wang ,  Ian A. Young

IPC: G06F12/0831 ,  G06F12/0875 ,  G06F12/0811

CPC classification number: G06F13/1642 ,  G06F12/0811

Abstract: A processor includes a processing core and a cache controller including a read queue and a separate write queue. The read queue is to buffer read requests of the processing core to a non-volatile memory, last level cache (NVM-LLC), and the write queue is to buffer write requests to the NVM-LLC. The cache controller is to detect whether the write queue is full. The cache controller further prioritizes a first order of sending requests to the NVM-LLC when the write queue contains an empty slot, the first order specifying a first pattern of sending the read requests before the write requests, and prioritizes a second order of sending requests to the NVM-LLC in response to a determination that the write queue is full, the second order specifying a second pattern of alternating between sending a write request from the write queue and a read request from the read queue.

公开(公告)号：US11387404B2

公开(公告)日：2022-07-12

申请号：US16130905

申请日：2018-09-13

Applicant: Intel Corporation

Inventor： Huichu Liu ,  Tanay Karnik ,  Sasikanth Manipatruni ,  Daniel Morris ,  Kaushik Vaidyanathan ,  Ian Young

IPC: G11C11/00 ,  H01L43/02 ,  H01L43/10 ,  H01L43/06 ,  G11C11/16 ,  G11C11/18

Abstract: An apparatus is provided which comprises one or more magnetoelectric spin orbit (MESO) minority gates with different peripheral complementary metal oxide semiconductor (CMOS) circuit techniques in the device layer including: (1) current mirroring, (2) complementary supply voltages, (3) asymmetrical transistor sizing, and (4) using transmission gates. These MESO minority gates use the multi-phase clock to prevent back propagation of current so that MESO gate can correctly process the input data.

公开(公告)号：US10748602B2

公开(公告)日：2020-08-18

申请号：US16079400

申请日：2016-03-23

Applicant: Intel Corporation

Inventor： Huichu Liu ,  Sasikanth Manipatruni ,  Daniel H. Morris ,  Kaushik Vaidyanathan ,  Niloy Mukherjee ,  Dmitri E. Nikonov ,  Ian Young ,  Tanay Karnik

IPC: G11C11/00 ,  G11C11/413 ,  G11C11/412 ,  G11C7/10 ,  G11C13/00 ,  G11C14/00 ,  G11C7/20

Abstract: One embodiment provides an apparatus. The apparatus includes a pair of nonvolatile resistive random access memory (RRAM) memory cells coupled to a volatile static RAM (SRAM) memory cell. The pair of nonvolatile RRAM memory cells includes a first RRAM memory cell and a second RRAM memory cell. The first RRAM memory cell includes a first resistive memory element coupled to a first bit line, and a first selector transistor coupled between the first resistive memory element and a first output node of the volatile SRAM memory cell. The second RRAM memory cell includes a second resistive memory element coupled to a second bit line, and a second selector transistor coupled between the second resistive memory element and a second output node of the volatile SRAM memory cell.

公开(公告)号：US20240220785A1

公开(公告)日：2024-07-04

申请号：US18408716

申请日：2024-01-10

Applicant: Intel Corporation

Inventor： Gautham Chinya ,  Huichu Liu ,  Arnab Raha ,  Debabrata Mohapatra ,  Cormac Brick ,  Lance Hacking

IPC: G06N3/063 ,  G06F9/38 ,  G06F9/448 ,  G06F9/50 ,  G06N5/04

CPC classification number: G06N3/063 ,  G06F9/3814 ,  G06F9/3877 ,  G06F9/4498 ,  G06F9/5027 ,  G06N5/04

Abstract: Methods and systems include a neural network system that includes a neural network accelerator comprising. The neural network accelerator includes multiple processing engines coupled together to perform arithmetic operations in support of an inference performed using the deep neural network system. The neural network accelerator also includes a schedule-aware tensor data distribution circuitry or software that is configured to load tensor data into the multiple processing engines in a load phase, extract output data from the multiple processing engines in an extraction phase, reorganize the extracted output data, and store the reorganized extracted output data to memory.

公开(公告)号：US11907827B2

公开(公告)日：2024-02-20

申请号：US16456707

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Gautham Chinya ,  Huichu Liu ,  Arnab Raha ,  Debabrata Mohapatra ,  Cormac Brick ,  Lance Hacking

IPC: G06N3/063 ,  G06N5/04 ,  G06F9/448 ,  G06F9/38 ,  G06F9/50

CPC classification number: G06N3/063 ,  G06F9/3814 ,  G06F9/3877 ,  G06F9/4498 ,  G06F9/5027 ,  G06N5/04

Abstract: Methods and systems include a neural network system that includes a neural network accelerator. The neural network accelerator includes multiple processing engines coupled together to perform arithmetic operations in support of an inference performed using the deep neural network system. The neural network accelerator also includes a schedule-aware tensor data distribution circuitry or software that is configured to load tensor data into the multiple processing engines in a load phase, extract output data from the multiple processing engines in an extraction phase, reorganize the extracted output data, and store the reorganized extracted output data to memory.

公开(公告)号：US11804851B2

公开(公告)日：2023-10-31

申请号：US16832804

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Gautham Chinya ,  Debabrata Mohapatra ,  Arnab Raha ,  Huichu Liu ,  Cormac Brick

IPC: H03M7/30 ,  G06F16/22 ,  G06N3/063 ,  G06N3/08 ,  G06N3/04

CPC classification number: H03M7/3082 ,  G06F16/2237 ,  G06N3/063 ,  G06N3/04 ,  G06N3/08

Abstract: Methods, systems, articles of manufacture, and apparatus are disclosed to decode zero-value-compression data vectors. An example apparatus includes: a buffer monitor to monitor a buffer for a header including a value indicative of compressed data; a data controller to, when the buffer includes compressed data, determine a first value of a sparse select signal based on (1) a select signal and (2) a first position in a sparsity bitmap, the first value of the sparse select signal corresponding to a processing element that is to process a portion of the compressed data; and a write controller to, when the buffer includes compressed data, determine a second value of a write enable signal based on (1) the select signal and (2) a second position in the sparsity bitmap, the second value of the write enable signal corresponding to the processing element that is to process the portion of the compressed data.

公开(公告)号：US20200228137A1

公开(公告)日：2020-07-16

申请号：US16832804

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Gautham Chinya ,  Debabrata Mohapatra ,  Arnab Raha ,  Huichu Liu ,  Cormac Brick

IPC: H03M7/30 ,  G06F16/22 ,  G06N3/063

Abstract: Methods, systems, articles of manufacture, and apparatus are disclosed to decode zero-value-compression data vectors. An example apparatus includes: a buffer monitor to monitor a buffer for a header including a value indicative of compressed data; a data controller to, when the buffer includes compressed data, determine a first value of a sparse select signal based on (1) a select signal and (2) a first position in a sparsity bitmap, the first value of the sparse select signal corresponding to a processing element that is to process a portion of the compressed data; and a write controller to, when the buffer includes compressed data, determine a second value of a write enable signal based on (1) the select signal and (2) a second position in the sparsity bitmap, the second value of the write enable signal corresponding to the processing element that is to process the portion of the compressed data.

公开(公告)号：US20200098415A1

公开(公告)日：2020-03-26

申请号：US16615780

申请日：2018-07-23

Applicant: Intel Corporation

Inventor： Huichu Liu ,  Sasikanth Manipatruni ,  Ian A. Young ,  Tanay Karnik ,  Daniel H. Morris ,  Kaushik Vaidyanathan

IPC: G11C11/22 ,  H01L27/11507 ,  H01L49/02

Abstract: Described is an apparatus to reduce or eliminate imprint charge, wherein the apparatus which comprises: a source line; a bit-line; a memory bit-cell coupled to the source line and the bit-line; a first multiplexer coupled to the bit-line; a second multiplexer coupled to the source-line; a first driver coupled to the first multiplexer; a second driver coupled to the second multiplexer; and a current source coupled to the first and second drivers.