中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

73 records (took 0.067 seconds)

    SYSTEM, APPARATUS AND METHOD FOR MULTI-OWNER TRANSFER OF OWNERSHIP OF A DEVICE
    51.
    发明申请
    SYSTEM, APPARATUS AND METHOD FOR MULTI-OWNER TRANSFER OF OWNERSHIP OF A DEVICE 审中-公开
    用于设备所有权的多业务转移的系统，装置和方法

    公开(公告)号：US20160364787A1

    公开(公告)日：2016-12-15

    申请号：US14865191

    申请日：2015-09-25

    Applicant: Intel Corporation

    Inventor： Jesse Walker ,  Ned M. Smith ,  Howard C. Herbert ,  Manoj R. Sastry

    IPC: G06Q30/06 ,  H04L9/32 ,  H04L29/06

    CPC classification number: G06Q30/0635 ,  H04L9/0891 ,  H04L9/3247 ,  H04L63/061 ,  H04L63/0823 ,  H04L63/0876 ,  H04W4/70 ,  H04W12/04

    Abstract: In one embodiment, a method includes: receiving, in a device, a first message to request transfer of ownership of the device from a current owner to a new owner, the device having a storage to store a first title including a device identifier for the device and an owner identifier for the current owner, the storage to further store a first root authorization key associated with the current owner; sending a second message from the device to the new owner, the second message including a hash value of the first title; and receiving a third message, in the device, the third message including a second title for the device, the second title generated by the new owner and including a new owner identifier, the second title comprising a concatenation of the first title, to enable ownership of the device to be transferred to the new owner.

    Abstract translation: 在一个实施例中，一种方法包括：在设备中接收第一消息以请求将设备的所有权从当前拥有者转移到新所有者，所述设备具有存储第一标题的存储器，所述第一标题包括用于 设备和当前所有者的所有者标识符，所述存储器进一步存储与当前所有者相关联的第一根授权密钥; 从所述设备向所述新所有者发送第二消息，所述第二消息包括所述第一标题的哈希值; 以及在所述设备中接收第三消息，所述第三消息包括所述设备的第二标题，由所述新所有者生成并包括新所有者标识符的所述第二标题，所述第二标题包括所述第一标题的级联以使所有权 的设备被转移到新的所有者。

    Method, apparatus, system for qualifying CPU transactions with security attributes
    52.
    发明授权
    Method, apparatus, system for qualifying CPU transactions with security attributes 有权
    用于对具有安全属性的CPU事务进行限定的方法，装置，系统

    公开(公告)号：US08959576B2

    公开(公告)日：2015-02-17

    申请号：US13828676

    申请日：2013-03-14

    Applicant: Intel Corporation

    Inventor： Manoj R. Sastry ,  Ioannis T. Schoinas ,  Daniel M. Cermak

    IPC: G06F21/62

    CPC classification number: G06F21/74 ,  G06F21/57 ,  G06F21/78

    Abstract: Method, apparatus, and system for qualifying CPU transactions with security attributes. Immutable security attributes are generated for transactions initiator by a CPU or processor core that identifying the execution mode of the CPU/core being trusted or untrusted. The transactions may be targeted to an Input/Output (I/O) device or system memory via which a protected asset may be accessed. Policy enforcement logic blocks are implemented at various points in the apparatus or system that allow or deny transactions access to protected assets based on the immutable security attributes generated for the transactions. In one aspect, a multiple-level security scheme is implemented under which a mode register is updated via a first transaction to indicate the CPU/core is operating in a trusted execution mode, and security attributes are generated for a second transaction using execution mode indicia in the mode register to verify the transaction is from a trusted initiator.

    Abstract translation: 用于对具有安全属性的CPU事务进行限定的方法，设备和系统。 由CPU或处理器核心为事务发起者生成不可变的安全属性，用于识别CPU /核心被信任或不可信任的执行模式。 这些事务可以被定向到可被访问受保护资产的输入/输出（I / O）设备或系统存储器。 策略执行逻辑块在设备或系统中的不同点实现，其允许或拒绝事务基于为事务生成的不可变安全属性而访问被保护资产。 在一个方面，实现多级安全方案，在该级别下，通过第一事务来更新模式寄存器以指示CPU /核心以可信执行模式运行，并且使用执行模式标记为第二事务生成安全属性 在模式寄存器中验证事务来自可信发起者。

    Technology to provide fault tolerance for elliptic curve digital signature algorithm engines
    53.
    发明授权
    Technology to provide fault tolerance for elliptic curve digital signature algorithm engines 有权

    公开(公告)号：US11940888B2

    公开(公告)日：2024-03-26

    申请号：US17447600

    申请日：2021-09-14

    Applicant: Intel Corporation

    Inventor： Santosh Ghosh ,  Marcio Juliato ,  Manoj R. Sastry

    IPC: G06F11/27 ,  G06F11/22 ,  H04L9/00 ,  H04L9/30 ,  H04L9/32

    CPC classification number: G06F11/27 ,  G06F11/2236 ,  H04L9/004 ,  H04L9/3066 ,  H04L9/3252 ,  H04L2209/84

    Abstract: A data processing system includes technology for detecting and tolerating faults. The data processing system comprises an electronic control unit (ECU) with a processing core and a fault-tolerant elliptic curve digital signature algorithm (ECDSA) engine. The fault-tolerant ECDSA engine comprises multiple verification state machines (VSMs). The data processing system also comprises nonvolatile storage in communication with the processing core and ECU software in the nonvolatile storage. The ECU software, when executed, enables the data processing system to operate as a node in a distributed data processing system, including receiving digitally signed messages from other nodes in the distributed data processing system. The ECU further comprises a known-answer built-in self-test unit (KA-BISTU). Also, the ECU software comprises fault-tolerant ECDSA engine (FTEE) management software which, when executed by the processing core, utilizes the KA-BISTU to periodically test the fault-tolerant ECDSA engine for faults. Other embodiments are described and claimed.

    SECURITY PLUGIN FOR A SYSTEM-ON-A-CHIP PLATFORM
    57.
    发明申请
    SECURITY PLUGIN FOR A SYSTEM-ON-A-CHIP PLATFORM 有权

    公开(公告)号：US20220405427A1

    公开(公告)日：2022-12-22

    申请号：US17679009

    申请日：2022-02-23

    Applicant: Intel Corporation

    Inventor： Manoj R. Sastry ,  Alpa Narendra Trivedi ,  Men Long

    IPC: G06F21/72 ,  G09C1/00 ,  G06F21/85 ,  H04L9/06 ,  H04L9/08

    Abstract: Systems and techniques for a System-on-a-Chip (SoC) security plugin are described herein. A component message may be received at an interconnect endpoint from an SoC component. The interconnect endpoint may pass the component message to a security component via a security interlink. The security component may secure the component message, using a cryptographic engine, to create a secured message. The secured message is delivered back to the interconnect endpoint via the security interlink and transmitted across the interconnect by the interconnect endpoint.

    Systems and methods for message assurance in vehicle systems
    58.
    发明授权
    Systems and methods for message assurance in vehicle systems 有权

    公开(公告)号：US11423162B2

    公开(公告)日：2022-08-23

    申请号：US16833200

    申请日：2020-03-27

    Applicant: Intel Corporation

    Inventor： Marcio Juliato ,  Shabbir Ahmed ,  Maria Soledad Elli ,  Christopher Noe Gutierrez ,  Vuk Lesi ,  Manoj R. Sastry ,  John Charles Weast ,  Liuyang Lily Yang

    IPC: G06F21/62 ,  G06F13/38

    Abstract: A vehicle control system, including an in-vehicle bus and a plurality of electronic control units (ECUs) coupled to the in-vehicle bus, wherein at least one ECU of the plurality of ECUs is configured to: receive, at a respective at least one ECU of the plurality of ECUs, a message in a message stream on the in-vehicle bus; evaluate the message to determine at least one of a confidence value of the security classification, a significance value of the message, or a bounds check value of the message; and determine in real-time to allow or deny the message to the vehicle control system based on at least one of the significance value of the message, the bounds check value of the message, or the confidence value of the security classification of the message, to provide a sanitized message stream to the vehicle control system.

    Technology To Provide Fault Tolerance For Elliptic Curve Digital Signature Algorithm Engines
    59.
    发明申请
    Technology To Provide Fault Tolerance For Elliptic Curve Digital Signature Algorithm Engines 有权

    公开(公告)号：US20220083439A1

    公开(公告)日：2022-03-17

    申请号：US17447600

    申请日：2021-09-14

    Applicant: Intel Corporation

    Inventor： Santosh Ghosh ,  Marcio Juliato ,  Manoj R. Sastry

    IPC: G06F11/27 ,  H04L9/30 ,  G06F11/22 ,  H04L9/32 ,  H04L9/00

    Abstract: A data processing system includes technology for detecting and tolerating faults. The data processing system comprises an electronic control unit (ECU) with a processing core and a fault-tolerant elliptic curve digital signature algorithm (ECDSA) engine. The fault-tolerant ECDSA engine comprises multiple verification state machines (VSMs). The data processing system also comprises nonvolatile storage in communication with the processing core and ECU software in the nonvolatile storage. The ECU software, when executed, enables the data processing system to operate as a node in a distributed data processing system, including receiving digitally signed messages from other nodes in the distributed data processing system. The ECU further comprises a known-answer built-in self-test unit (KA-BISTU). Also, the ECU software comprises fault-tolerant ECDSA engine (FTEE) management software which, when executed by the processing core, utilizes the KA-BISTU to periodically test the fault-tolerant ECDSA engine for faults. Other embodiments are described and claimed.

    BUS-OFF ATTACK PREVENTION CIRCUIT
    60.
    发明申请
    BUS-OFF ATTACK PREVENTION CIRCUIT 有权

    公开(公告)号：US20220078201A1

    公开(公告)日：2022-03-10

    申请号：US17529020

    申请日：2021-11-17

    Applicant: Intel Corporation

    Inventor： Marcio Rogerio Juliato ,  Shabbir AHMED ,  Santosh GHOSH ,  Christopher GUTIERREZ ,  Manoj R. Sastry

    IPC: H04L29/06 ,  H04L12/40

    Abstract: Various systems and methods for bus-off attack detection are described herein. An electronic device for bus-off attack detection and prevention includes bus-off prevention circuitry coupled to a protected node on a bus, the bus-off prevention circuitry to: detect a transmitted message from the protected node to the bus; detect a bit mismatch of the transmitted message on the bus; suspend further transmissions from the protected node while the bus is analyzed; determine whether the bit mismatch represents a bus fault or an active attack against the protected node; and signal the protected node indicating whether a fault has occurred.

Patent Agency Ranking