公开(公告)号：US20120070976A1

公开(公告)日：2012-03-22

申请号：US13234558

申请日：2011-09-16

Applicant: Tae-Hyun KIM ,  Kyung-Hyun Kim ,  Jae-Hwang Sim ,  Jae-Jin Shin ,  Jong-Heun Lim ,  Hyun-Min Park

Inventor： Tae-Hyun KIM ,  Kyung-Hyun Kim ,  Jae-Hwang Sim ,  Jae-Jin Shin ,  Jong-Heun Lim ,  Hyun-Min Park

IPC: H01L21/28

CPC classification number: H01L27/11526 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11529 ,  H01L27/11573

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of preliminary gate structures, forming a capping layer pattern on sidewalls of the plurality of preliminary gate structures, and forming a blocking layer on top surfaces of the plurality of preliminary gate structures and the capping layer pattern such that a void is formed therebetween. The method also includes removing the blocking layer and an upper portion of the capping layer pattern such that at least the upper sidewalls of the plurality of preliminary gate structures are exposed, and a lower portion of the capping layer pattern remains on lower sidewalls of the preliminary gate structures. The method further includes forming a conductive layer on at least the upper sidewalls of the plurality of preliminary gate structures, reacting the conductive layer with the preliminary gate structures, and forming an insulation layer having an air gap therein.

Abstract translation: 一种制造半导体器件的方法包括：形成多个初步栅极结构，在多个预选栅极结构的侧壁上形成覆盖层图案，以及在多个预选栅极结构的顶表面上形成阻挡层，并且覆盖层 使得它们之间形成空隙。 该方法还包括去除阻挡层和覆盖层图案的上部，使得至少多个预选栅极结构的上侧壁被暴露，并且覆盖层图案的下部保留在预备的栅极结构的下侧壁上 门结构。 所述方法还包括在所述多个预选择门结构的至少上侧壁上形成导电层，使所述导电层与所述预选栅极结构反应，以及在其中形成具有气隙的绝缘层。

公开(公告)号：US20100090349A1

公开(公告)日：2010-04-15

申请号：US12639542

申请日：2009-12-16

Applicant: Sang-Yong Park ,  Jae-Hwang Sim ,  Young-Ho Lee ,  Kyung-Lyul Moon ,  Jae-Kwan Park

Inventor： Sang-Yong Park ,  Jae-Hwang Sim ,  Young-Ho Lee ,  Kyung-Lyul Moon ,  Jae-Kwan Park

IPC: H01L23/48

CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/823456 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region. The feature layer is etched using the mask layer patterns as an etch mask in the second region and using the spacers as an etch mask in the first region to provide a feature layer pattern having fine features in the first region and broad features in the second region.

Abstract translation: 在形成半导体器件的方法中，在衬底上提供特征层，并且在特征层上设置掩模层。 掩模层的一部分在半导体器件的第一区域被去除，其中特征层的精细特征将被定位，掩模层保留在半导体器件的第二区域中，其中特征层的广泛特征将是 位于。 模具掩模图案设置在第一区域中的特征层和第二区域中的掩模层上。 间隔层设置在第一区域和第二区域中的模具掩模图案上。 执行蚀刻工艺以蚀刻间隔层，使得间隔物保留在模具掩模图案的图案特征的侧壁处，并且蚀刻第二区域中的掩模层以在第二区域中提供掩模层图案。 使用掩模层图案作为第二区域中的蚀刻掩模蚀刻特征层，并且在第一区域中使用间隔物作为蚀刻掩模来提供在第一区域中具有精细特征的特征层图案，并且在第二区域中具有广泛特征 。

公开(公告)号：US20090311861A1

公开(公告)日：2009-12-17

申请号：US12290420

申请日：2008-10-30

Applicant: Sang-Yong Park ,  Jae-Hwang Sim ,  Young-Ho Lee ,  Kyung-Lyul Moon ,  Jae-Kwan Park

Inventor： Sang-Yong Park ,  Jae-Hwang Sim ,  Young-Ho Lee ,  Kyung-Lyul Moon ,  Jae-Kwan Park

IPC: H01L21/302

CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/823456 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region. The feature layer is etched using the mask layer patterns as an etch mask in the second region and using the spacers as an etch mask in the first region to provide a feature layer pattern having fine features in the first region and broad features in the second region.

Abstract translation: 在形成半导体器件的方法中，在衬底上提供特征层，并且在特征层上设置掩模层。 掩模层的一部分在半导体器件的第一区域被去除，其中特征层的精细特征将被定位，掩模层保留在半导体器件的第二区域中，其中特征层的广泛特征将是 位于。 模具掩模图案设置在第一区域中的特征层和第二区域中的掩模层上。 间隔层设置在第一区域和第二区域中的模具掩模图案上。 执行蚀刻工艺以蚀刻间隔层，使得间隔物保留在模具掩模图案的图案特征的侧壁处，并且蚀刻第二区域中的掩模层以在第二区域中提供掩模层图案。 使用掩模层图案作为第二区域中的蚀刻掩模蚀刻特征层，并且在第一区域中使用间隔物作为蚀刻掩模来提供在第一区域中具有精细特征的特征层图案，并且在第二区域中具有广泛特征 。

公开(公告)号：US20080160693A1

公开(公告)日：2008-07-03

申请号：US11945477

申请日：2007-11-27

Applicant: Jae-Hwang Sim ,  Yong-Sik Yim ,  Ki-Nam Kim ,  Jae-Kwan Park

Inventor： Jae-Hwang Sim ,  Yong-Sik Yim ,  Ki-Nam Kim ,  Jae-Kwan Park

IPC: H01L21/8247

CPC classification number: H01L27/11524 ,  H01L27/115 ,  H01L27/11521 ,  Y10S438/954

Abstract: A method of forming a non-volatile memory device includes forming first mask patterns, which can have relatively large distances therebetween. A distance regulating layer is formed that conformally covers the first mask patterns. Second mask patterns are formed in grooves on the distance regulating layer between the first mask patterns.

Abstract translation: 形成非易失性存储器件的方法包括形成第一掩模图案，它们之间的距离可以相对较大。 形成保形地覆盖第一掩模图案的距离调节层。 在第一掩模图案之间的距离调节层的凹槽中形成第二掩模图案。