公开(公告)号：US06627950B1

公开(公告)日：2003-09-30

申请号：US08851608

申请日：1997-05-05

Applicant: Constantin Bulucea ,  Rebecca Rossen

Inventor： Constantin Bulucea ,  Rebecca Rossen

IPC: H01L2976

CPC classification number: H01L29/7813 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/7811 ,  Y10S148/126

Abstract: Power MOSFET apparatus, and method for its production, that suppresses voltage breakdown near the gate, using a polygon-shaped trench in which the gate is positioned, using a shaped deep body junction that partly lies below the trench bottom, and using special procedures for growth of gate oxide at various trench corners.

Abstract translation: 功率MOSFET器件及其制造方法，使用位于沟槽底部下方的成形深体结，使用位于栅极的多边形沟槽来抑制栅极附近的电压击穿，并使用特殊程序 栅极氧化物在各种沟角处的生长。

公开(公告)号：US06576966B1

公开(公告)日：2003-06-10

申请号：US09535434

申请日：2000-03-23

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L2976

CPC classification number: H01L29/66659 ,  H01L21/823807 ,  H01L27/0928 ,  H01L29/1045 ,  H01L29/7835

Abstract: An asymmetric insulated-gate field-effect transistor (40) is configured in an asymmetric lightly doped drain structure that alleviates hot-carrier effects and enables the source characteristics to be decoupled from the drain characteristics. The transistor has a multi-part channel formed with an output portion (46), which adjoins the drain zone, and a more heavily doped input portion (42), which adjoins the source zone (44). The drain zone contains a main portion (52) and a more lightly doped extension (50) that meets the output channel portion. The drain extension extends at least as far below the upper semiconductor surface as the main drain portion so as to help reduce hot-carrier effects. The input channel portion is situated in a threshold body zone (53) whose doping determines the threshold voltage. The provision of a lightly doped source extension is avoided so that improving the drain characteristics does not harm the source characteristics, and vice versa.

Abstract translation: 非对称绝缘栅场效应晶体管（40）配置在不对称轻掺杂漏极结构中，其减轻热载流子效应，并使得源极特性能够与漏极特性去耦合。 晶体管具有形成有与漏极区相邻的输出部分（46）和与源区（44）相邻的更重掺杂的输入部分（42）的多部分通道。 漏区包含与输出通道部分相遇的主要部分（52）和更轻掺杂的延伸部（50）。 漏极延伸部至少与主漏极部分的上半导体表面一样远，以帮助减少热载流子效应。 输入通道部分位于阈值体区（53）中，其掺杂决定了阈值电压。 避免提供轻掺杂的源延伸，从而改善漏极特性不会损害源特性，反之亦然。

公开(公告)号：US5441900A

公开(公告)日：1995-08-15

申请号：US308698

申请日：1994-09-19

Applicant: Constantin Bulucea ,  Esin Dermirlioglu ,  Sheldon Aronowitz

Inventor： Constantin Bulucea ,  Esin Dermirlioglu ,  Sheldon Aronowitz

IPC: H01L27/092 ,  H01L21/265

CPC classification number: H01L27/0921 ,  Y10S148/023 ,  Y10S438/904 ,  Y10S438/917

Abstract: A unique approach to suppressing latchup in CMOS structures is described. Atomic species that exhibit midgap levels in silicon and satisfy the criteria for localized action and electrical compatibility can be implanted to suppress the parasitic bipolar behavior which causes latchup. Reduction of minority carrier lifetime can be achieved in critical parasitic bipolar regions that, by CMOS construction are outside the regions of active MOS devices. One way to accomplish this goal is to use the source/drain masks to locally implant the minority carrier lifetime reducer (MCLR) before the source/drain dopants are implanted. This permits the MCLR to be introduced at different depths or even to be different species, of the n and p-channel transistors. Another way to accomplish this goal requires that a blanket MCLR implant be done very early in the process, before isolation oxidation, gate oxidation or active threshold implants are done.

Abstract translation: 描述了抑制CMOS结构中的闭锁的独特方法。 可以植入在硅中显示中间水平并满足局部作用和电相容性标准的原子物质，以抑制引起闭锁的寄生双极性行为。 通过CMOS结构在有源MOS器件区域之外的临界寄生双极区域可以实现少数载流子寿命的降低。 实现这一目标的一个方法是在源极/漏极掺杂剂被植入之前，使用源极/漏极掩模来局部注入少数载流子寿命衰减器（MCLR）。 这允许MCLR在n沟道晶体管和p沟道晶体管的不同深度或者甚至不同的物种中被引入。 实现这一目标的另一种方法是要求在隔离氧化，栅极氧化或活性阈值植入完成之前，在该过程中非常早地完成覆盖MCLR植入物。

公开(公告)号：US08610207B2

公开(公告)日：2013-12-17

申请号：US13298283

申请日：2011-11-16

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L21/8238

CPC classification number: H01L21/823892 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

Abstract: An insulated-gate field-effect transistor (220U) utilizes an empty-well region for achieving high performance. The concentration of the body dopant reaches a maximum at a subsurface location no more than 10 times deeper below the upper semiconductor surface than the depth of one of a pair of source/drain zones (262 and 264), decreases by at least a factor of 10 in moving from the subsurface location along a selected vertical line (136U) through that source/drain zone to the upper semiconductor surface, and has a logarithm that decreases substantially monotonically and substantially inflectionlessly in moving from the subsurface location along the vertical line to that source/drain zone. Each source/drain zone has a main portion (262M or 264M) and a more lightly doped lateral extension (262E or 264E). Alternatively or additionally, a more heavily doped pocket portion (280) of the body material extends along one of the source/drain zones.

Abstract translation: 绝缘栅场效应晶体管（220U）利用空阱区实现高性能。 身体掺杂物的浓度在上半导体表面下方比在一对源/漏区（262和264）之一的深度不超过10倍的地下位置处达到最大值，减小至少一个因子 10沿着沿着选择的垂直线（136U）通过该源极/漏极区域移动到上半导体表面的地下位置移动，并且具有从沿着垂直线的地下位置移动到基本单调和基本上无穷地减小的对数， 源/漏区。 每个源/漏区具有主要部分（262M或264M）和更轻掺杂的横向延伸（262E或264E）。 替代地或另外地，主体材料的更重掺杂的凹穴部分（280）沿着源极/漏极区域中的一个延伸。

公开(公告)号：US08502273B2

公开(公告)日：2013-08-06

申请号：US12908458

申请日：2010-10-20

Applicant: Sandeep Bahl ,  Constantin Bulucea

Inventor： Sandeep Bahl ,  Constantin Bulucea

IPC: H01L29/778 ,  H01L21/338

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/66462

Abstract: The buffer breakdown of a group III-N HEMT on a p-type Si substrate is significantly increased by forming an n-well in the p-type Si substrate to lie directly below the metal drain region of the group III-N HEMT. The n-well forms a p-n junction which becomes reverse biased during breakdown, thereby increasing the buffer breakdown by the reverse-biased breakdown voltage of the p-n junction and allowing the substrate to be grounded. The buffer layer of a group III-N HEMT can also be implanted with n-type and p-type dopants which are aligned with the p-n junction to minimize any leakage currents at the junction between the substrate and the buffer layer.

Abstract translation: 通过在p型Si衬底中形成n阱以直接位于III-NHEMT族金属漏极区的下方，在p型Si衬底上的III-N HEMT组的缓冲击穿显着增加。 n阱形成在击穿期间变得反向偏置的p-n结，从而通过p-n结的反向偏置击穿电压增加缓冲器击穿，并允许衬底接地。 III-N型HEMT的缓冲层也可以注入与p-n结对准的n型和p型掺杂剂，以最小化衬底和缓冲层之间的接合处的任何漏电流。

公开(公告)号：US20130126983A1

公开(公告)日：2013-05-23

申请号：US13298283

申请日：2011-11-16

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L29/78

CPC classification number: H01L21/823892 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

Abstract: An insulated-gate field-effect transistor (220U) utilizes an empty-well region for achieving high performance. The concentration of the body dopant reaches a maximum at a subsurface location no more than 10 times deeper below the upper semiconductor surface than the depth of one of a pair of source/drain zones (262 and 264), decreases by at least a factor of 10 in moving from the subsurface location along a selected vertical line (136U) through that source/drain zone to the upper semiconductor surface, and has a logarithm that decreases substantially monotonically and substantially inflectionlessly in moving from the subsurface location along the vertical line to that source/drain zone. Each source/drain zone has a main portion (262M or 264M) and a more lightly doped lateral extension (262E or 264E). Alternatively or additionally, a more heavily doped pocket portion (280) of the body material extends along one of the source/drain zones.

Abstract translation: 绝缘栅场效应晶体管（220U）利用空阱区实现高性能。 身体掺杂物的浓度在上半导体表面下方比在一对源/漏区（262和264）之一的深度不超过10倍的地下位置处达到最大值，减小至少一个因子 10沿着沿着选择的垂直线（136U）通过该源极/漏极区域移动到上半导体表面的地下位置移动，并且具有从沿着垂直线的地下位置移动到基本单调和基本上无穷地减小的对数， 源/漏区。 每个源/漏区具有主要部分（262M或264M）和更轻掺杂的横向延伸（262E或264E）。 替代地或另外地，主体材料的更重掺杂的凹穴部分（280）沿着源极/漏极区域中的一个延伸。

公开(公告)号：US20120181626A1

公开(公告)日：2012-07-19

申请号：US13298284

申请日：2011-11-16

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/1203

Abstract: An insulated-gate field-effect transistor (220U) is provided with an empty-well region for achieving high performance. The concentration of the body dopant reaches a maximum at a subsurface location no more than 10 times deeper below the upper semiconductor surface than the depth of one of a pair of source/drain zones (262 and 264), decreases by at least a factor of 10 in moving from the subsurface location along a selected vertical line (136U) through that source/drain zone to the upper semiconductor surface, and has a logarithm that decreases substantially monotonically and substantially inflectionlessly in moving from the subsurface location along the vertical line to that source/drain zone. Each source/drain zone has a main portion (262M or 264M) and a more lightly doped lateral extension (262E or 264E). Alternatively or additionally, a more heavily doped pocket portion (280) of the body material extends along one of the source/drain zones.

Abstract translation: 绝缘栅场效应晶体管（220U）具有用于实现高性能的空井区域。 身体掺杂物的浓度在上半导体表面下方比在一对源/漏区（262和264）之一的深度不超过10倍的地下位置处达到最大值，减小至少一个因子 10沿着沿着选择的垂直线（136U）通过该源极/漏极区域移动到上半导体表面的地下位置移动，并且具有从沿着垂直线的地下位置移动到基本单调和基本上无穷地基本上单调减小的对数， 源/漏区。 每个源/漏区具有主要部分（262M或264M）和更轻掺杂的横向延伸（262E或264E）。 替代地或另外地，主体材料的更重掺杂的凹穴部分（280）沿着源极/漏极区域中的一个延伸。

公开(公告)号：US07642574B2

公开(公告)日：2010-01-05

申请号：US11981481

申请日：2007-10-31

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L27/088

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/092 ,  H01L27/1203 ,  H01L27/1207

Abstract: An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) has a hypoabrupt vertical dopant profile below one (104 or 264) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108 or 268). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone. The body material preferably includes a more heavily doped pocket portion (120 or 280) situated along the other source/drain zone (102 or 262). The combination of the hypoabrupt vertical dopant profile below the first-mentioned source/drain zone, normally serving as the drain, and the pocket portion along the second-mentioned source/drain zone, normally serving as the source, enables the resultant asymmetric transistor to be especially suitable for high-speed analog applications.

Abstract translation: 绝缘栅场效应晶体管（100,100V，140,150,150V，160,170,170V，180,180V，190,210,210W，220,220U，220V，220W，380或480）具有 低于其源极/漏极区（104或264）的垂直掺杂剂分布，用于减小源极/漏极区与邻接体材料（108或268）之间的pn结的寄生电容。 特别地，限定主体材料的导电类型的半导体掺杂剂的浓度在从该源极/漏极区向下移动到下面的主体材料位置时不小于10倍深度的上方增加至少10倍 半导体表面比该源/漏区。 主体材料优选地包括沿着另一个源极/漏极区（102或262）设置的更重掺杂的凹穴部分（120或280）。 通常用作漏极的第一提及的源极/漏极区下方的低破坏垂直掺杂物分布以及通常用作源的第二次提供的源极/漏极区的凹穴部分的组合使得所得的不对称晶体管能够 特别适用于高速模拟应用。

公开(公告)号：US20080308878A1

公开(公告)日：2008-12-18

申请号：US11981481

申请日：2007-10-31

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L27/088 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/092 ,  H01L27/1203 ,  H01L27/1207

Abstract: An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) has a hypoabrupt vertical dopant profile below one (104 or 264) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108 or 268). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone. The body material preferably includes a more heavily doped pocket portion (120 or 280) situated along the other source/drain zone (102 or 262). The combination of the hypoabrupt vertical dopant profile below the first-mentioned source/drain zone, normally serving as the drain, and the pocket portion along the second-mentioned source/drain zone, normally serving as the source, enables the resultant asymmetric transistor to be especially suitable for high-speed analog applications.

Abstract translation: 绝缘栅场效应晶体管（100,100V，140,150,150V，160,170,170V，180,180V，190,210,210W，220,220U，220V，220W，380或480）具有 低于其源极/漏极区（104或264）的垂直掺杂剂分布，用于减小源极/漏极区与邻接体材料（108或268）之间的pn结的寄生电容。 特别地，限定主体材料的导电类型的半导体掺杂剂的浓度在从该源极/漏极区向下移动到下面的主体材料位置时不小于10倍深度的上方增加至少10倍 半导体表面比该源/漏区。 主体材料优选地包括沿着另一个源极/漏极区（102或262）设置的更重掺杂的凹穴部分（120或280）。 通常用作漏极的第一提及的源极/漏极区下方的低破坏垂直掺杂物分布以及通常用作源的第二次提供的源极/漏极区的凹穴部分的组合使得所得的不对称晶体管能够 特别适用于高速模拟应用。

公开(公告)号：US07235862B2

公开(公告)日：2007-06-26

申请号：US09903059

申请日：2001-07-10

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L29/93

CPC classification number: H01L29/93 ,  H01L27/0808 ,  H01L29/7391 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243

Abstract: A semiconductor junction varactor utilizes gate enhancement for enabling the varactor to achieve a high ratio of maximum capacitance to minimum capacitance.

Abstract translation: 半导体结变容二极管利用栅极增强来使变容二极管实现最大电容与最小电容的高比率。