公开(公告)号：US5441900A

公开(公告)日：1995-08-15

申请号：US308698

申请日：1994-09-19

Applicant: Constantin Bulucea ,  Esin Dermirlioglu ,  Sheldon Aronowitz

Inventor： Constantin Bulucea ,  Esin Dermirlioglu ,  Sheldon Aronowitz

IPC: H01L27/092 ,  H01L21/265

CPC classification number: H01L27/0921 ,  Y10S148/023 ,  Y10S438/904 ,  Y10S438/917

Abstract: A unique approach to suppressing latchup in CMOS structures is described. Atomic species that exhibit midgap levels in silicon and satisfy the criteria for localized action and electrical compatibility can be implanted to suppress the parasitic bipolar behavior which causes latchup. Reduction of minority carrier lifetime can be achieved in critical parasitic bipolar regions that, by CMOS construction are outside the regions of active MOS devices. One way to accomplish this goal is to use the source/drain masks to locally implant the minority carrier lifetime reducer (MCLR) before the source/drain dopants are implanted. This permits the MCLR to be introduced at different depths or even to be different species, of the n and p-channel transistors. Another way to accomplish this goal requires that a blanket MCLR implant be done very early in the process, before isolation oxidation, gate oxidation or active threshold implants are done.

Abstract translation: 描述了抑制CMOS结构中的闭锁的独特方法。 可以植入在硅中显示中间水平并满足局部作用和电相容性标准的原子物质，以抑制引起闭锁的寄生双极性行为。 通过CMOS结构在有源MOS器件区域之外的临界寄生双极区域可以实现少数载流子寿命的降低。 实现这一目标的一个方法是在源极/漏极掺杂剂被植入之前，使用源极/漏极掩模来局部注入少数载流子寿命衰减器（MCLR）。 这允许MCLR在n沟道晶体管和p沟道晶体管的不同深度或者甚至不同的物种中被引入。 实现这一目标的另一种方法是要求在隔离氧化，栅极氧化或活性阈值植入完成之前，在该过程中非常早地完成覆盖MCLR植入物。

公开(公告)号：US5384477A

公开(公告)日：1995-01-24

申请号：US28456

申请日：1993-03-09

Applicant: Constantin Bulucea ,  Esin Dermirlioglu ,  Sheldon Aronowitz

Inventor： Constantin Bulucea ,  Esin Dermirlioglu ,  Sheldon Aronowitz

IPC: H01L27/092 ,  H01L29/78

CPC classification number: H01L27/0921 ,  Y10S148/023 ,  Y10S438/904 ,  Y10S438/917

Abstract: A unique approach to suppressing latchup in CMOS structures is described. Atomic species that exhibit midgap levels in silicon and satisfy the criteria for localized action and electrical compatibility can be implanted to suppress the parasitic bipolar behavior Which causes latchup. Reduction of minority carrier lifetime can be achieved in critical parasitic bipolar regions that, by CMOS construction are outside the regions of active MOS devices. One way to accomplish this goal is to use the source/drain masks to locally implant the minority carrier lifetime reducer (MCLR) before the source/drain dopants are implanted. This permits the MCLR to be introduced at different depths or even to be different species, of the n and p-channel transistors. Another way to accomplish this goal requires that a blanket MCLR implant be done very early in the process, before isolation oxidation, gate oxidation or active threshold implants are done.

Abstract translation: 描述了抑制CMOS结构中的闭锁的独特方法。 可以植入在硅中显示中等水平并满足局部作用和电相容性标准的原子物质，以抑制引起闭锁的寄生双极性行为。 通过CMOS结构在有源MOS器件区域之外的临界寄生双极区域可以实现少数载流子寿命的降低。 实现这一目标的一个方法是在源极/漏极掺杂剂被植入之前，使用源极/漏极掩模来局部注入少数载流子寿命衰减器（MCLR）。 这允许MCLR在n沟道晶体管和p沟道晶体管的不同深度或者甚至不同的物种中被引入。 实现这一目标的另一种方法是要求在隔离氧化，栅极氧化或活性阈值植入完成之前，在该过程中非常早地完成覆盖MCLR植入物。

公开(公告)号：US07132336B1

公开(公告)日：2006-11-07

申请号：US10123263

申请日：2002-04-15

Applicant: Sheldon Aronowitz ,  Vladimir Zubkov ,  Grace S. Sun

Inventor： Sheldon Aronowitz ,  Vladimir Zubkov ,  Grace S. Sun

IPC: H01L21/336

CPC classification number: H01L29/513 ,  H01L21/265 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/31155 ,  H01L29/517 ,  H01L29/78

Abstract: An improved semiconductor memory structure and methods for its fabrication are disclosed. The memory structure includes a semiconductor substrate having a dielectric region formed over a channel region. A doped region is formed between a top portion and a bottom portion of the dielectric region. This doped region includes a suitable electron affinity material. A gate electrode is connected with the top of the dielectric region. In some embodiments, suitable electron affinity materials are introduced into the doped region using implantation techniques. In another embodiment, the electron affinity material is introduced into the doped region using plasma treatment of the dielectric region and the redeposition of additional dielectric material on top of the dielectric region and doped region.

Abstract translation: 公开了一种改进的半导体存储器结构及其制造方法。 存储器结构包括具有形成在沟道区上的电介质区域的半导体衬底。 在电介质区域的顶部和底部之间形成掺杂区域。 该掺杂区域包括合适的电子亲和性材料。 栅电极与电介质区域的顶部连接。 在一些实施方案中，使用注入技术将合适的电子亲和性材料引入掺杂区域。 在另一个实施方案中，使用电介质区域的等离子体处理和在介电区域和掺杂区域的顶部上再沉积附加电介质材料将电子亲和性材料引入掺杂区域。

公开(公告)号：US06822308B2

公开(公告)日：2004-11-23

申请号：US10600665

申请日：2003-06-20

Applicant: Sheldon Aronowitz ,  Vladimir Zubkov

Inventor： Sheldon Aronowitz ,  Vladimir Zubkov

IPC: H01L2900

CPC classification number: H01L21/306 ,  H01L21/31

Abstract: A method of chemically altering a silicon surface and associated dielectric materials are disclosed.

Abstract translation: 公开了一种化学改变硅表面和相关介电材料的方法。

公开(公告)号：US06649219B2

公开(公告)日：2003-11-18

申请号：US09792691

申请日：2001-02-23

Applicant: Sheldon Aronowitz ,  Vladimir Zubkov

Inventor： Sheldon Aronowitz ,  Vladimir Zubkov

IPC: C23C1640

CPC classification number: H01L21/02126 ,  C01B33/126 ,  C23C16/401 ,  H01L21/02211 ,  H01L21/3121 ,  H01L21/31629 ,  H01L21/31633 ,  Y02P20/129

Abstract: The invention provides a process for forming a low k fluorine and carbon-containing silicon oxide dielectric material by reacting with an oxidizing agent one or more silanes containing one or more organofluoro silanes having the formula SiR1R2R3R4, where: (a) R1 is selected from H, a 3 to 10 carbon alkyl, and an alkoxy; (b) R2 contains at least one C atom bonded to at least one F atom, and no aliphatic C—H bonds; and (c) R3 and R4 are selected from H, alkyl, alkoxy, a moiety containing at least one C atom bonded to at least one F atom, and ((L)Si(R5)(R6))n(R7); where n ranges from 1 to 10; L is O or CFR8; each n R5 and R6 is selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom; R7 is selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom; and each R8 is selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom. Also provided is a low dielectric constant fluorine and carbon-doped silicon oxide dielectric material for use in an integrated circuit structure which contains: silicon atoms bonded to oxygen atoms; silicon atoms bonded to carbon atoms; and carbon atoms bonded to fluorine atoms; where the dielectric material also has a characteristic selected from: (a) the presence of at least one C—C bond; (b) the presence of at least one carbon atom bonded to from 1 to 2 fluorine atoms; and (c) the presence of at least one silicon atom bonded to from 0 to 2 oxygen atoms.

公开(公告)号：US06627556B1

公开(公告)日：2003-09-30

申请号：US10131431

申请日：2002-04-24

Applicant: Sheldon Aronowitz ,  Vladimir Zubkov

Inventor： Sheldon Aronowitz ,  Vladimir Zubkov

IPC: H01L21302

CPC classification number: H01L21/306 ,  H01L21/31

Abstract: A method of chemically altering a silicon surface and associated dielectric materials are disclosed.

公开(公告)号：US06613651B1

公开(公告)日：2003-09-02

申请号：US09654689

申请日：2000-09-05

Applicant: Helmut Puchner ,  Sheldon Aronowitz

Inventor： Helmut Puchner ,  Sheldon Aronowitz

IPC: H01L2176

CPC classification number: H01L21/7621

Abstract: A method of forming a narrow isolation structure in a semiconducting substrate. The isolation structure is a trench that has a bottom and sidewalls, and that is to be filled with an isolating material. The isolating material has desired electrical properties and desired chemical properties, and is substantially reactively grown from the semiconducting substrate. A precursor material layer is formed on the bottom of the trench and on the sidewalls of the trench. The precursor material layer has electrical properties and chemical properties that are substantially similar to the desired electrical properties and the desired chemical properties of the isolating material. A substantial portion of the precursor material layer is removed from the bottom of the trench to expose the semiconducting substrate at the bottom of the trench, while leaving a substantial portion of the precursor material layer on the sidewalls of the trench. The isolating material is reactively grown in the trench, where the isolating material preferentially grows from the exposed semiconducting substrate at the bottom of the trench at a first rate. The precursor material layer at least partially inhibits formation of the isolating material from the semiconducting substrate at the sidewalls of the trench. The isolating material forms from the sidewalls of the trench at a second rate, where the first rate is substantially higher than the second rate. Thus, by forming a precursor layer that inhibits formation of the isolation material at the sidewalls of the trench, the isolation material preferentially grows from the bottom of the trench rather than expanding sideways from the sidewalls of the trench, which tends to widen the isolation structure. Because the precursor layer has properties that are substantially similar to those that are desired in the isolation material, the precursor layer remains at the sidewalls of the trench near the edge of the isolation structure. Therefore, the isolation structure functions as desired, but is narrower than it otherwise would be, if the precursor layer had not been formed.

公开(公告)号：US06566262B1

公开(公告)日：2003-05-20

申请号：US10004461

申请日：2001-11-01

Applicant: Paul Rissman ,  Richard Schinella ,  Sheldon Aronowitz ,  Vladimir Zubkov

Inventor： Paul Rissman ,  Richard Schinella ,  Sheldon Aronowitz ,  Vladimir Zubkov

IPC: H01L2144

CPC classification number: H01L23/53238 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76886 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the invention include a capping layer of alloy material formed over a copper-containing layer, the alloy configured to prevent diffusion of copper through the capping layer. In another embodiment the alloy capping layer is self-aligned to the underlying conducting layer. Specific embodiments include capping layers formed of alloys of copper with materials including but not limited to calcium, strontium, barium, and other alkaline earth metals, as well as materials from other groups, for example, cadmium or selenium. The invention also includes methods for forming an alloy capping layer on a copper-containing conducting structure. One such method includes providing a substrate having formed thereon electrically conducting layer comprised of a copper-containing material and forming an alloy capping layer on the electrically conducting layer. In another method embodiment, forming the alloy capping layer includes forming a self-aligned capping layer over the conducting layer. In another method embodiment for forming a capping layer on a copper-containing conducting structure, a substrate having formed thereon electrically conducting layer comprised of a copper-containing material is provided. A layer of reactive material is then formed on the surface of the substrate. This is followed by reacting a portion of the layer of reactive material with the copper-containing material of the conducting layer to form an alloy material on the conducting layer. Unalloyed reactive material is removed from the substrate by heating the substrate to a temperature where the unalloyed reactive material desorbs from the surface of the substrate but where the alloy material remains in place on the substrate surface thereby forming a self-aligned capping layer. In another embodiment, the process is repeated iteratively until a capping layer having the desired thickness is formed.

Abstract translation: 本发明的实施方案包括在含铜层上形成的合金材料的覆盖层，该合金构造成防止铜通过覆盖层的扩散。 在另一个实施例中，合金覆盖层与下面的导电层自对准。 具体实施方案包括由铜的合金与包括但不限于钙，锶，钡和其它碱土金属的材料形成的封盖层，以及来自其它基团的材料，例如镉或硒。 本发明还包括在含铜导电结构上形成合金覆盖层的方法。 一种这样的方法包括提供其上形成有由含铜材料构成的导电层并在导电层上形成合金覆盖层的衬底。 在另一方法实施例中，形成合金覆盖层包括在导电层上形成自对准覆盖层。在用于在含铜导电结构上形成覆盖层的另一方法实施例中，其上形成有导电层的基板包括 提供含铜材料。 然后在衬底的表面上形成一层反应性材料。 然后使反应性材料层的一部分与导电层的含铜材料反应，以在导电层上形成合金材料。 通过将衬底加热到​​非合金反应物质从衬底表面脱附的温度，但是合金材料保留在衬底表面上的适当位置，从而形成非对准的覆盖层，从衬底去除非合金反应性材料。 在另一个实施方案中，迭代地重复该过程，直到形成具有所需厚度的覆盖层。

公开(公告)号：US06331468B1

公开(公告)日：2001-12-18

申请号：US09076399

申请日：1998-05-11

Applicant: Sheldon Aronowitz ,  Helmut Puchner ,  Ravindra A. Kapre ,  James P. Kimball

Inventor： Sheldon Aronowitz ,  Helmut Puchner ,  Ravindra A. Kapre ,  James P. Kimball

IPC: H01L21336

CPC classification number: H01L21/28185 ,  H01L21/2652 ,  H01L21/28202 ,  H01L21/28247 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/6659

Abstract: A process is described for using a silicon layer as an implant and out-diffusion layer, for forming defect-free source/drain regions in a semiconductor substrate, and also for subsequent formation of silicon nitride spacers. A nitrogen-containing dopant barrier layer is first formed over a single crystal semiconductor substrate by nitridating either a previously formed gate oxide layer, or a silicon layer formed over the gate oxide layer, to form a barrier layer comprising either a silicon, oxygen, and nitrogen compound or a compound of silicon and nitrogen. The nitridating may be carried out using a nitrogen plasma followed by an anneal. A polysilicon gate electrode is then formed over this barrier layer, and the exposed portions of the barrier layer remaining are removed. An amorphous silicon layer of predetermined thickness is then formed over the substrate and polysilicon gate electrode. This amorphous layer is then implanted with a dopant capable of forming a source/drain region in the underlying silicon substrate by subsequent diffusion of the implanted dopant from the amorphous silicon layer into the substrate. The structure is then annealed to diffuse the dopant from the implanted silicon layer into the substrate to form the desired source/drain regions and into the polysilicon gate electrode to dope the polysilicon. The annealing further serves to cause the amorphous silicon layer to crystalize to polycrystalline silicon (polysilicon). In one embodiment, the polysilicon layer is then nitridized to convert it to a silicon nitride layer which is then patterned to form silicon nitride spacers on the sidewalls of the polysilicon gate electrode to electrically insulate the gate electrode from the source/drain regions. The process may be further modified to also create LDD or HDD source/drain regions in the substrate (depending on the concentration of the dopant), using multiple implants into the same silicon layer or by the sequential use of several silicon layers, each of which is used as an implantation and out-diffusion layer.

公开(公告)号：US5858864A

公开(公告)日：1999-01-12

申请号：US939350

申请日：1997-09-29

Applicant: Sheldon Aronowitz ,  James Kimball

Inventor： Sheldon Aronowitz ,  James Kimball

IPC: H01L21/265

CPC classification number: H01L21/26506 ,  H01L21/26513

Abstract: Formation of a barrier region in a single crystal group IV semiconductor substrate at a predetermined spacing from a doped region in the substrate is described to prevent or inhibit migration of dopant materials from an adjacent doped region through the barrier region. By implantation of group IV materials into a semiconductor substrate to a predetermined depth in excess of the depth of a doped region, a barrier region can be created in the semiconductor to prevent migration of the dopants from the doped region through the barrier region. The treatment of the single crystal substrate with the group IV material is carried out at a dosage and energy level sufficient to provide such a barrier region in the semiconductor substrate, but insufficient to result in amorphization (destruction) of the single crystal lattice of the semiconductor substrate.

Abstract translation: 描述了以与衬底中的掺杂区域预定间隔的单晶IV IV半导体衬底中的阻挡区域的形成，以防止或抑制掺杂剂材料通过阻挡区域从相邻掺杂区域的迁移。 通过将IV族材料注入到半导体衬底中至超过掺杂区域的深度的预定深度，可以在半导体中产生阻挡区域，以防止掺杂剂从掺杂区域迁移穿过阻挡区域。 用IV族材料处理单晶衬底以足以在半导体衬底中提供这种势垒区域的剂量和能级进行，但不足以导致半导体单晶晶格的非晶化（破坏） 基质。