公开(公告)号：US20110267888A1

公开(公告)日：2011-11-03

申请号：US13181750

申请日：2011-07-13

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze

IPC分类号： G11C16/04

CPC分类号： G11C16/16 ,  G11C11/5635 ,  G11C16/0483

摘要： A technique for erasing a non-volatile memory applies a p-well voltage to a substrate and drives select gate voltages to accurately control the select gate voltage to improve write-erase endurance. Source and drain side select gates of a NAND string are driven at levels to optimize endurance. In one approach, the select gates are driven at specific levels throughout an erase operation, in concert with the p-well voltage.

摘要翻译： 擦除非易失性存储器的技术将p阱电压施加到衬底并驱动选择栅极电压以精确地控制选择栅极电压以提高写入擦除耐久性。 NAND串的源极和漏极侧选择栅极被驱动，以优化耐久性。 在一种方法中，与p阱电压一致，在擦除操作期间以特定电平驱动选择栅极。

公开(公告)号：US20110122692A1

公开(公告)日：2011-05-26

申请号：US12625883

申请日：2009-11-25

申请人： Deepanshu Dutta ,  Gerrit Jan Hemink

发明人： Deepanshu Dutta ,  Gerrit Jan Hemink

IPC分类号： G11C16/10 ,  G11C16/34

CPC分类号： G11C16/3454 ,  G11C11/5628 ,  G11C16/3459 ,  G11C2211/5621

摘要： A method and non-volatile storage system are provided in which programming speed is increased by reducing the number of verify operations, while maintaining a narrow threshold voltage distribution. A programming scheme performs a verify operation at an offset level, before a verify level of a target data state is reached, such as to slow down programming. However, it is not necessary to perform verify operations at both the offset and target levels at all times. In a first programming phase, verify operations are performed for a given data state only at the target verify level. In a second programming phase, verify operations are performed for offset and target verify levels. In a third programming phase, verify operations are again performed only at the target verify level. Transitions between phases can be predetermined, based on programming pulse number, or adaptive.

摘要翻译： 提供了一种方法和非易失性存储系统，其中通过减少验证操作的数量来增加编程速度，同时保持窄的阈值电压分布。 在达到目标数据状态的验证级别之前，编程方案在偏移级别执行验证操作，例如减慢编程。 但是，始终不必在偏移量和目标电平两者上执行验证操作。 在第一个编程阶段，仅在目标验证级别对给定数据状态执行验证操作。 在第二个编程阶段，对偏移和目标验证电平执行验证操作。 在第三个编程阶段，仅在目标验证级别再次执行验证操作。 相位之间的转换可以根据编程脉冲数或自适应来预先确定。

公开(公告)号：US07876611B2

公开(公告)日：2011-01-25

申请号：US12188629

申请日：2008-08-08

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Yingda Dong ,  Henry Chin ,  Toru Ishigaki

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze ,  Yingda Dong ,  Henry Chin ,  Toru Ishigaki

IPC分类号： G11C11/34

CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3418

摘要： Capacitive coupling from storage elements on adjacent bit lines is compensated by adjusting voltages applied to the adjacent bit lines. An initial rough read is performed to ascertain the data states of the bit line-adjacent storage elements, and during a subsequent fine read, bit line voltages are set based on the ascertained states and the current control gate read voltage which is applied to a selected word line. When the current control gate read voltage corresponds to a lower data state than the ascertained state of an adjacent storage element, a compensating bit line voltage is used. Compensation of coupling from a storage element on an adjacent word line can also be provided by applying different read pass voltages to the adjacent word line, and obtaining read data using a particular read pass voltage which is identified based on a data state of the word line-adjacent storage element.

摘要翻译： 通过调整施加到相邻位线的电压来补偿相邻位线上的存储元件的电容耦合。 执行初始粗略读取以确定位线相邻存储元件的数据状态，并且在随后的精细读取期间，基于确定的状态和施加到所选择的电流控制栅极读取电压的电流控制栅极读取电压来设置位线电压 字线。 当电流控制栅极读取电压对应于比相邻存储元件的确定状态低的数据状态时，使用补偿位线电压。 也可以通过对相邻字线应用不同的读通过电压来提供来自相邻字线上的存储元件的耦合的补偿，并且使用基于字线的数据状态来识别的特定读通过电压来获得读取数据 相邻存储元件。

公开(公告)号：US20100238730A1

公开(公告)日：2010-09-23

申请号：US12406014

申请日：2009-03-17

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/16 ,  G11C11/5635 ,  G11C16/0483

摘要： A technique for erasing a non-volatile memory applies a p-well voltage to a substrate and drives or floats select gate voltages to accurately control the select gate voltage to improve write-erase endurance. Source and drain side select gates of a NAND string are driven at levels to optimize endurance. In one approach, the select gates float after being driven at a specific initial level, to reach a specific, optimal final level. In another approach, the select gates are driven at specific levels throughout an erase operation, in concert with the p-well voltage. In another approach, onset of select gate floating is delayed while the p-well voltage ramps up. In another approach, p-well voltage is ramped up in two steps, and the select gates are not floated until the second ramp begins. Floating can be achieved by raising the drive voltage to cut off pass gates of the select gates.

摘要翻译： 擦除非易失性存储器的技术将p阱电压施加到衬底并且驱动或浮动选择栅极电压以精确地控制选择栅极电压以改善写入擦除耐久性。 NAND串的源极和漏极侧选择栅极被驱动，以优化耐久性。 在一种方法中，选择门在被特定初始级别驱动之后浮动，以达到特定的最佳最终级别。 在另一种方法中，与p阱电压一致，在擦除操作期间，选择栅极以特定电平驱动。 在另一种方法中，选择栅极浮动的开始被延迟，而p阱电压上升。 在另一种方法中，p阱电压以两个步骤升高，并且在第二个斜坡开始之前，选择栅极不浮动。 可以通过提高驱动电压来切断选通门的通孔来实现浮动。

公开(公告)号：US20100110792A1

公开(公告)日：2010-05-06

申请号：US12398368

申请日：2009-03-05

申请人： Jeffrey W. Lutze ,  Deepanshu Dutta

发明人： Jeffrey W. Lutze ,  Deepanshu Dutta

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3454 ,  G11C2211/5621

摘要： A programming technique reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. One aspect groups alternate pairs of adjacent bit lines into first and second sets. Dual programming pulses are applied to a selected word line. The first set of bit lines is programmed during the first pulse, and the second set of bit lines is programmed during the second pulse. A verify operation is then performed for all bit lines. When a particular bit line is inhibited, at least one of its neighbor bit lines will also be inhibited so that the channel of the particular bit line will be sufficiently boosted. Another aspect programs every third bit line separately. A modified layout allows adjacent pairs of bit lines to be sensed using odd-even sensing circuitry.

摘要翻译： 编程技术通过使用选择的位线模式进行编程来减少一组非易失性存储元件中的编程干扰，这增加了禁止信道的钳位升压电位以避免编程干扰。 一个方面将交替的相邻位线对组合成第一和第二组。 双编程脉冲被施加到选定的字线。 第一组位线在第一脉冲期间被编程，并且第二组位线在第二脉冲期间被编程。 然后对所有位线执行验证操作。 当特定位线被禁止时，其相邻位线中的至少一个也将被禁止，使得特定位线的通道将被充分提升。 另一个方面分别编写每第三个位线。 修改的布局允许使用奇偶校验感测电路来感测相邻的位线对。

公开(公告)号：US20090282184A1

公开(公告)日：2009-11-12

申请号：US12118446

申请日：2008-05-09

申请人： Deepanshu Dutta ,  Jeffrey W. Lutze

发明人： Deepanshu Dutta ,  Jeffrey W. Lutze

IPC分类号： G06F12/02

CPC分类号： G11C16/0483 ,  B05B11/3098 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3454 ,  G11C2211/5621

摘要： Optimized verify and read pass voltages are obtained to improve read accuracy in a non-volatile storage device. The optimized voltages account for changes in unselected storage element resistance when the storage elements become programmed. This change in resistance is referred to as a front pattern effect. In one approach, the verify pass voltage is higher than the read pass voltage, and a common verify voltage is applied on the source and drain sides of a selected word line. In other approaches, different verify pass voltages are applied on the source and drain sides of the selected word line. An optimization process can include determining a metric for different sets of verify and read pass voltages. The metric can indicate threshold voltage width, read errors or a decoding time or number of iterations of an ECC decoding engine.

摘要翻译： 获得优化的验证和读取通过电压，以提高非易失性存储设备的读取精度。 当存储元件变为编程时，优化的电压表示未选择的存储元件电阻的变化。 这种电阻变化被称为前模式效应。 在一种方法中，验证通过电压高于读取通过电压，并且在所选字线的源极和漏极侧施加公共验证电压。 在其他方法中，不同的验证通过电压施加在所选字线的源极和漏极侧。 优化过程可以包括确定不同组的验证和读取通过电压的度量。 该度量可以指示ECC解码引擎的阈值电压宽度，读取错误或解码时间或迭代次数。