公开(公告)号：US06670663B2

公开(公告)日：2003-12-30

申请号：US10233535

申请日：2002-09-04

申请人： Yoo-Sang Hwang ,  Sang-Ho Song ,  Byung Jun Park ,  Tae Young Chung

发明人： Yoo-Sang Hwang ,  Sang-Ho Song ,  Byung Jun Park ,  Tae Young Chung

IPC分类号： H01L27108

CPC分类号： H01L27/10852 ,  H01L21/76895 ,  H01L27/10897 ,  H01L28/82 ,  H01L28/91

摘要： A method for manufacturing a cell capacitor includes a step of forming an upper electrode and a trench for the lower electrode simultaneously in a single mask step. Further steps for manufacturing a cell capacitor includes forming a storage node contact by employing a predefined plate silicon layer and forming a capacitor dielectric using the storage contact node, as a result, it becomes possible to resolve “lift-off” problems, twin-bit failures, and misalignment.

公开(公告)号：US06548853B1

公开(公告)日：2003-04-15

申请号：US10076234

申请日：2002-02-13

申请人： In-Seak Hwang ,  Si-Youn Kim ,  Yoo-Sang Hwang ,  Hoon Jung

发明人： In-Seak Hwang ,  Si-Youn Kim ,  Yoo-Sang Hwang ,  Hoon Jung

IPC分类号： H01L27108

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/87 ,  H01L28/91

摘要： Cylindrical capacitors and methods of fabricating the same are provided. The cylindrical capacitor includes a cylindrical storage node stacked on a semiconductor substrate. The cylindrical storage node has a base and a stepped sidewall located on the base. The stepped sidewall has at least two sub-sidewalls, which are sequentially stacked, and at least one joint portion that connects a lower sidewall of the sub-sidewalls to an upper sidewall stacked on the lower sidewall. An upper diameter of the respective sub-sidewalls is greater than a lower diameter thereof. Also, the upper diameter of the lower sidewall is greater than the lower diameter of the upper sidewall stacked on the lower sidewall. The method of fabricating the cylindrical storage node having a stepped sidewall includes sequentially forming a plurality of molding layers over a semiconductor substrate. An etch rate of a lower molding layer of the plurality of molding layers being faster than that of an upper molding layer on the lower molding layer with respect to a predetermined etchant. The plurality of molding layers are patterned to form a preliminary storage node hole that exposes a portion of the semiconductor substrate. The patterned molding layers are isotropically etched using the etchant, thereby forming a storage node hole. Therefore, the storage node hole has a stepped sidewall profile. A conformal conductive layer is then formed on the substrate and the conductive layer is planarized until a top surface of the molding layers is exposed.

摘要翻译： 提供了圆柱形电容器及其制造方法。 圆柱形电容器包括堆叠在半导体衬底上的圆柱形存储节点。 圆柱形存储节点具有底座和位于基座上的阶梯式侧壁。 阶梯状侧壁具有依次层叠的至少两个副侧壁和将副侧壁的下侧壁与层叠在下侧壁上的上侧壁连接的至少一个接合部。 各副侧壁的上径大于其下直径。 此外，下侧壁的上直径大于堆叠在下侧壁上的上侧壁的下直径。 制造具有阶梯状侧壁的圆柱形存储节点的方法包括在半导体衬底上顺序形成多个成型层。 多个成型层中的下模塑层的蚀刻速率比相对于预定蚀刻剂的下成型层上的上模塑层的蚀刻速率快。 图案化多个成型层以形成露出半导体衬底的一部分的预备存储节点孔。 使用蚀刻剂对图案化的成型层进行各向同性蚀刻，从而形成存储节点孔。 因此，存储节点孔具有梯级侧壁轮廓。 然后在衬底上形成共形导电层，并且导电层被平坦化，直到模制层的顶表面露出。

公开(公告)号：US06518671B1

公开(公告)日：2003-02-11

申请号：US09699591

申请日：2000-10-30

申请人： Won-Suk Yang ,  Yoo-Sang Hwang ,  Hong-Sik Jeong ,  Ki-Nam Kim

发明人： Won-Suk Yang ,  Yoo-Sang Hwang ,  Hong-Sik Jeong ,  Ki-Nam Kim

IPC分类号： H02L2348

CPC分类号： H01L21/76897 ,  H01L21/76829 ,  H01L21/76834 ,  H01L27/10882 ,  H01L27/10894

摘要： An etch-stop layer is selectively provided between layers of a multiple-layered circuit in a selective manner so as to allow for outgassing of impurities during subsequent fabrication processes. The etch-stop layer is formed over an underlying stud so as to serve as an alignment target during formation of an overlying stud formed in an upper layer. In this manner multiple-layered circuits, for example memory devices, can be fabricated in relatively dense

摘要翻译： 选择性地在多层电路的层之间选择性地提供蚀刻停止层，以便允许随后的制造过程中的杂质脱气。 蚀刻停止层形成在下面的螺柱上，以便在形成在上层中的上覆螺柱的形成期间用作对准目标。 以这种方式，可以相对致密地制造多层电路，例如存储器件

公开(公告)号：US06489195B1

公开(公告)日：2002-12-03

申请号：US09702795

申请日：2000-11-01

申请人： Yoo-Sang Hwang ,  Byung-Jun Park

发明人： Yoo-Sang Hwang ,  Byung-Jun Park

IPC分类号： H01L21265

CPC分类号： H01L28/90 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885

摘要： A DRAM cell is provided, along with a method for fabricating such a DRAM cell. A protection layer pattern is formed to cover a common drain region of first and second access transistors. Storage node holes are then formed to expose each source region of the first and second access transistors, by using an etching insulator that has an etching selectivity with respect to the protection layer. Accordingly, even if there is a misalignment of the storage node holes to thesource regions, the common drain region is not exposed by the misaligned storage node holes because of the presence of the protection layer pattern.

摘要翻译： 提供DRAM单元以及用于制造这种DRAM单元的方法。 形成保护层图案以覆盖第一和第二存取晶体管的公共漏极区域。 然后通过使用相对于保护层具有蚀刻选择性的蚀刻绝缘体，形成存储节点孔以暴露第一和第二存取晶体管的每个源极区域。 因此，即使存在存储节点孔与源极区域不对准，由于保护层图案的存在，公共漏极区域也不会被未对准的存储节点孔露出。