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    Method for manufacturing semiconductor device having increased effective channel length
    3.
    发明授权
    Method for manufacturing semiconductor device having increased effective channel length 有权
    具有增加有效通道长度的半导体器件的制造方法

    公开(公告)号：US06815300B2

    公开(公告)日：2004-11-09

    申请号：US10427172

    申请日：2003-04-30

    申请人： Hong-Sik Jeong ,  Ki-Nam Kim ,  Yoo-Sang Hwang

    发明人： Hong-Sik Jeong ,  Ki-Nam Kim ,  Yoo-Sang Hwang

    IPC分类号： H01L21336

    CPC分类号： H01L27/10873 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10888 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

    摘要： In one embodiment, a plurality of gate structures including gate electrodes and insulating layers covering the gate electrodes are formed on a semiconductor substrate. Impurity ions at a low dose for forming a source/drain region are implanted into the semiconductor substrate, using the gate structures as a mask. First insulating spacers are formed on the sidewalls of the gate structures and second insulating spacers are formed on the first insulating spacers. Thereafter, impurity ions at a high dose are implanted into the semiconductor substrate, using the first and second insulating spacers as a mask. Then, the second insulating spacers are removed. Therefore, contact resistance and characteristics of the transistors can be improved by adjusting an effective channel length and contact areas.

    摘要翻译： 在一个实施例中，在半导体衬底上形成包括栅电极和覆盖栅电极的绝缘层的多个栅极结构。 使用栅极结构作为掩模，将用于形成源极/漏极区域的低剂量的杂质离子注入到半导体衬底中。 第一绝缘垫片形成在栅极结构的侧壁上，第二绝缘垫片形成在第一绝缘垫片上。 此后，使用第一和第二绝缘间隔物作为掩模，将高剂量的杂质离子注入到半导体衬底中。 然后，去除第二绝缘间隔物。 因此，可以通过调节有效沟道长度和接触面积来提高晶体管的接触电阻和特性。

    Semiconductor memory device and method for manufacturing the same
    5.
    发明申请
    Semiconductor memory device and method for manufacturing the same 失效
    半导体存储器件及其制造方法

    公开(公告)号：US20050167717A1

    公开(公告)日：2005-08-04

    申请号：US11080032

    申请日：2005-03-14

    申请人： Won-Suk Yang ,  Sang-Hoo Song ,  Ki-Nam Kim ,  Hong-Sik Jeong

    发明人： Won-Suk Yang ,  Sang-Hoo Song ,  Ki-Nam Kim ,  Hong-Sik Jeong

    IPC分类号： H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L27/108 ,  H01L29/94

    CPC分类号： H01L27/10894 ,  H01L21/76895 ,  H01L23/485 ,  H01L27/10882 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A conductive portion connects a lower conductive layer formed on a semiconductor substrate provided in a first interlayer insulating layer to an upper conductive layer formed on the lower conductive layer, and provided in a second interlayer insulating layer. This portion is divided into at least one plug and a pad. At least one plug is formed in a first interlayer insulating layer and the lower part of a second interlayer insulating layer. The second interlayer insulating layer is divided into a plurality of interlayer insulating layers so that upper and lower widths of the divided plugs formed in the divided portion of the second interlayer insulating layer are not greatly different from each other. The pad formed on the upper portion of the second interlayer insulating layer has an upper width such that the upper conductive layer connected to the pad is not undesirably connected to an adjacent upper conductive layer via the pad.

    摘要翻译： 导电部分将形成在第一层间绝缘层中的半导体衬底上形成的下导电层连接到形成在下导电层上的上导电层，并设置在第二层间绝缘层中。 该部分被分成至少一个插头和垫。 在第一层间绝缘层和第二层间绝缘层的下部形成至少一个插塞。 第二层间绝缘层被分成多个层间绝缘层，使得形成在第二层间绝缘层的分割部分中的分隔插塞的上下宽度彼此不是很大的不同。 形成在第二层间绝缘层的上部的焊盘具有上部宽度，使得连接到焊盘的上部导电层不会通过焊盘不期望地连接到相邻的上部导电层。

    Semiconductor memory device and method for manufacturing the same
    7.
    发明授权
    Semiconductor memory device and method for manufacturing the same 失效
    半导体存储器件及其制造方法

    公开(公告)号：US07462523B2

    公开(公告)日：2008-12-09

    申请号：US11080032

    申请日：2005-03-14

    申请人： Won-Suk Yang ,  Sang-Hoo Song ,  Ki-Nam Kim ,  Hong-Sik Jeong

    发明人： Won-Suk Yang ,  Sang-Hoo Song ,  Ki-Nam Kim ,  Hong-Sik Jeong

    IPC分类号： H01L29/72

    CPC分类号： H01L27/10894 ,  H01L21/76895 ,  H01L23/485 ,  H01L27/10882 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A conductive portion connects a lower conductive layer formed on a semiconductor substrate provided in a first interlayer insulating layer to an upper conductive layer formed on the lower conductive layer, and provided in a second interlayer insulating layer. This portion is divided into at least one plug and a pad. At least one plug is formed in a first interlayer insulating layer and the lower part of a second interlayer insulating layer. The second interlayer insulating layer is divided into a plurality of interlayer insulating layers so that upper and lower widths of the divided plugs formed in the divided portion of the second interlayer insulating layer are not greatly different from each other. The pad formed on the upper portion of the second interlayer insulating layer has an upper width such that the upper conductive layer connected to the pad is not undesirably connected to an adjacent upper conductive layer via the pad.

    摘要翻译： 导电部分将形成在第一层间绝缘层中的半导体衬底上形成的下导电层连接到形成在下导电层上的上导电层，并设置在第二层间绝缘层中。 该部分被分成至少一个插头和垫。 在第一层间绝缘层和第二层间绝缘层的下部形成至少一个插塞。 第二层间绝缘层被分成多个层间绝缘层，使得形成在第二层间绝缘层的分割部分中的分隔插塞的上下宽度彼此不是很大的不同。 形成在第二层间绝缘层的上部的焊盘具有上部宽度，使得连接到焊盘的上部导电层不会通过焊盘不期望地连接到相邻的上部导电层。

    Bit line landing pad and borderless contact on bit line stud with etch stop layer and manufacturing method thereof
    9.
    发明授权
    Bit line landing pad and borderless contact on bit line stud with etch stop layer and manufacturing method thereof 有权
    带蚀刻停止层的位线接头上的位线着陆焊盘和无边界触点及其制造方法

    公开(公告)号：US06350649B1

    公开(公告)日：2002-02-26

    申请号：US09699849

    申请日：2000-10-30

    申请人： Hong-Sik Jeong ,  Won-Suk Yang ,  Ki-Nam Kim

    发明人： Hong-Sik Jeong ,  Won-Suk Yang ,  Ki-Nam Kim

    IPC分类号： H01L218242

    CPC分类号： H01L27/10894 ,  H01L27/10855

    摘要： An etch-stop layer is selectively provided between layers of a multiple-layered circuit so as to allow for outgassing of impurities during subsequent fabrication processes. The etch-stop layer is formed over an underlying stud so as to serve as an alignment target during formation of an overlying stud formed in an upper layer to be coupled to the underlying stud. In this manner multiple-layered circuits, for example memory devices, can be fabricated in relatively dense configurations.

    摘要翻译： 在多层电路的层之间选择性地设置蚀刻停止层，以便在随后的制造过程中允许杂质脱气。 蚀刻停止层形成在下面的螺柱上，以便在形成在要连接到下面的螺柱的上层中的上覆螺柱的形成期间用作对准目标。 以这种方式，可以以相对致密的配置制造多层电路，例如存储器件。

    Methods of operating magnetic random access memory device using spin injection and related devices
    10.
    发明授权
    Methods of operating magnetic random access memory device using spin injection and related devices 有权
    使用自旋注入和相关器件操作磁性随机存取存储器件的方法

    公开(公告)号：US07164598B2

    公开(公告)日：2007-01-16

    申请号：US11201495

    申请日：2005-08-11

    申请人： Won-Cheol Jeong ,  Ki-Nam Kim ,  Hong-Sik Jeong ,  Gi-Tae Jeong ,  Jae-Hyun Park

    发明人： Won-Cheol Jeong ,  Ki-Nam Kim ,  Hong-Sik Jeong ,  Gi-Tae Jeong ,  Jae-Hyun Park

    IPC分类号： G11C11/00 ,  G11C11/15

    CPC分类号： G11C11/16

    摘要： Methods are provided for operating a magnetic random access memory device including a memory cell having a magnetic tunnel junction structure on a substrate. In particular, a writing current pulse may be provided through the magnetic tunnel junction structure, and a writing magnetic field pulse may be provided through the magnetic tunnel junction structure. In addition, at least a portion of the writing magnetic field pulse may be overlapping in time with respect to at least a portion of the writing current pulse, and at least a portion of the writing current pulse and/or at least a portion of the writing magnetic field pulse may be non-overlapping in time with respect to the other. Related devices are also discussed.

    摘要翻译： 提供了用于操作包括在衬底上具有磁性隧道结结构的存储单元的磁性随机存取存储器件的方法。 特别地，可以通过磁性隧道结结构提供写入电流脉冲，并且可以通过磁性隧道结结构提供写入磁场脉冲。 此外，写入磁场脉冲的至少一部分可以相对于写入电流脉冲的至少一部分在时间上重叠，并且写入电流脉冲的至少一部分和/或至少一部分 写入磁场脉冲可能在时间上相对于另一个不重叠。 还讨论了相关设备。