公开(公告)号：US06479343B1

公开(公告)日：2002-11-12

申请号：US09510247

申请日：2000-02-22

申请人： Yoo-Sang Hwang ,  Sang-Ho Song ,  Byung Jun Park ,  Tae Young Chung

发明人： Yoo-Sang Hwang ,  Sang-Ho Song ,  Byung Jun Park ,  Tae Young Chung

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L21/76895 ,  H01L27/10897 ,  H01L28/82 ,  H01L28/91

摘要： A method for manufacturing a cell capacitor includes a step of forming an upper electrode and a trench for the lower electrode simultaneously in a single mask step. Further steps for manufacturing a cell capacitor includes forming a storage node contact by employing a predefined plate silicon layer and forming a capacitor dielectric using the storage contact node, as a result, it becomes possible to resolve “lift-off” problems, twin-bit failures, and misalignment.

摘要翻译： 电容器电容器的制造方法包括在单个掩模步骤中同时形成用于下电极的上电极和沟槽的步骤。 用于制造电池电容器的其它步骤包括通过采用预定义的硅板形成存储节点接触并且使用存储接触节点形成电容器电介质，结果，可以解决“剥离”问题，双位 失败和失调。

公开(公告)号：US06670663B2

公开(公告)日：2003-12-30

申请号：US10233535

申请日：2002-09-04

申请人： Yoo-Sang Hwang ,  Sang-Ho Song ,  Byung Jun Park ,  Tae Young Chung

发明人： Yoo-Sang Hwang ,  Sang-Ho Song ,  Byung Jun Park ,  Tae Young Chung

IPC分类号： H01L27108

CPC分类号： H01L27/10852 ,  H01L21/76895 ,  H01L27/10897 ,  H01L28/82 ,  H01L28/91

摘要： A method for manufacturing a cell capacitor includes a step of forming an upper electrode and a trench for the lower electrode simultaneously in a single mask step. Further steps for manufacturing a cell capacitor includes forming a storage node contact by employing a predefined plate silicon layer and forming a capacitor dielectric using the storage contact node, as a result, it becomes possible to resolve “lift-off” problems, twin-bit failures, and misalignment.

公开(公告)号：US06720269B2

公开(公告)日：2004-04-13

申请号：US10347219

申请日：2003-01-21

申请人： Byung-Jun Park ,  Yoo-Sang Hwang

发明人： Byung-Jun Park ,  Yoo-Sang Hwang

IPC分类号： H01L21311

CPC分类号： H01L27/10855 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10885

摘要： A self-aligned contact structure in a semiconductor device and methods for making such contact structure wherein the semiconductor device has a semiconductor substrate having active regions, an interlayer insulating layer covering the semiconductor substrate excluding at least a portion of each active region, at least two parallel interconnections on the interlayer insulating layer, at least one active region being relatively disposed between the at least two parallel interconnections, each interconnection having sidewalls, bottom and a width (x), a mask pattern having a top portion (z) and a bottom portion (y) formed on each interconnection, and a conductive layer pattern penetrating at least a portion of the interlayer insulating layer between the mask pattern and being electrically connected to at least one active region, wherein: x≦y≦z and x

摘要翻译： 半导体器件中的自对准接触结构以及用于制造这种接触结构的方法，其中半导体器件具有具有有源区的半导体衬底，覆盖半导体衬底的层间绝缘层，不包括每个有源区的至少一部分，至少两个 所述层间绝缘层上的平行互连，至少一个有源区相对设置在所述至少两个平行互连之间，每个互连具有侧壁，底部和宽度（x），具有顶部（z）和底部 形成在每个互连上的部分（y），以及穿透掩模图案之间的层间绝缘层的至少一部分并且与至少一个有源区电连接的导电层图案，其中：x <= y <= z和x

公开(公告)号：US06534813B1

公开(公告)日：2003-03-18

申请号：US09889588

申请日：2001-08-02

申请人： Byung-Jun Park ,  Yoo-Sang Hwang

发明人： Byung-Jun Park ,  Yoo-Sang Hwang

IPC分类号： H01L27108

CPC分类号： H01L27/10855 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10885

摘要： A self-aligned contact structure in a semiconductor device and methods of forming the same are provided, wherein the self-aligned contact structure in the semiconductor device comprises a semiconductor substrate having active regions; an interlayer insulating layer covering the semiconductor substrate excluding at least a portion of each active region; at least two parallel interconnections on the interlayer insulating layer, at least one active region being relatively disposed between the at least two parallel interconnections, each interconnection having sidewalls, a bottom and a width (x); a mask pattern having a top portion of width (z) and a bottom portion of width (y) formed on each interconnection; and a conductive layer pattern penetrating at least a portion of the interlayer insulating layer between the mask pattern and being electrically connected to at least one active region, wherein x≦y≦z and x

摘要翻译： 提供半导体器件中的自对准接触结构及其形成方法，其中半导体器件中的自对准接触结构包括具有有源区的半导体衬底; 覆盖半导体衬底的层间绝缘层，所述层间绝缘层不包括每个有源区的至少一部分; 在所述层间绝缘层上的至少两个平行互连，至少一个有源区相对设置在所述至少两个平行互连之间，每个互连具有侧壁，底部和宽度（x）; 具有形成在每个互连上的宽度（z）的顶部和宽度（y）的底部的掩模图案; 以及导电层图案，其穿透所述掩模图案之间的所述层间绝缘层的至少一部分并与至少一个有源区电连接，其中x <= y

公开(公告)号：US06703657B2

公开(公告)日：2004-03-09

申请号：US10189737

申请日：2002-07-08

申请人： Yoo-Sang Hwang ,  Byung-Jun Park

发明人： Yoo-Sang Hwang ,  Byung-Jun Park

IPC分类号： H01L27108

CPC分类号： H01L28/90 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885

摘要： A DRAM cell is provided, along with a method for fabricating such a DRAM cell. A protection layer pattern is formed to cover a common drain region of first and second access transistors. Storage node holes are then formed to expose each source region of the first and second access transistors, by using an etching insulator that has an etching selectivity with respect to the protection layer. Accordingly, even if there is a misalignment of the storage node holes to the source regions, the common drain region is not exposed by the misaligned storage node holes because of the presence of the protection layer pattern.

摘要翻译： 提供DRAM单元以及用于制造这种DRAM单元的方法。 形成保护层图案以覆盖第一和第二存取晶体管的公共漏极区域。 然后通过使用相对于保护层具有蚀刻选择性的蚀刻绝缘体，形成存储节点孔以暴露第一和第二存取晶体管的每个源极区域。 因此，即使存在存储节点孔与源极区域不对准，由于保护层图案的存在，共同漏极区域也不会被未对准的存储节点孔露出。

公开(公告)号：US06489195B1

公开(公告)日：2002-12-03

申请号：US09702795

申请日：2000-11-01

申请人： Yoo-Sang Hwang ,  Byung-Jun Park

发明人： Yoo-Sang Hwang ,  Byung-Jun Park

IPC分类号： H01L21265

CPC分类号： H01L28/90 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885

摘要： A DRAM cell is provided, along with a method for fabricating such a DRAM cell. A protection layer pattern is formed to cover a common drain region of first and second access transistors. Storage node holes are then formed to expose each source region of the first and second access transistors, by using an etching insulator that has an etching selectivity with respect to the protection layer. Accordingly, even if there is a misalignment of the storage node holes to thesource regions, the common drain region is not exposed by the misaligned storage node holes because of the presence of the protection layer pattern.

摘要翻译： 提供DRAM单元以及用于制造这种DRAM单元的方法。 形成保护层图案以覆盖第一和第二存取晶体管的公共漏极区域。 然后通过使用相对于保护层具有蚀刻选择性的蚀刻绝缘体，形成存储节点孔以暴露第一和第二存取晶体管的每个源极区域。 因此，即使存在存储节点孔与源极区域不对准，由于保护层图案的存在，公共漏极区域也不会被未对准的存储节点孔露出。

公开(公告)号：US06613621B2

公开(公告)日：2003-09-02

申请号：US09803244

申请日：2001-03-09

申请人： Hyung-Soo Uh ,  Kyu-Hynn Lee ,  Tae-Young Chung ,  Ki-Nam Kim ,  Yoo-Sang Hwang

发明人： Hyung-Soo Uh ,  Kyu-Hynn Lee ,  Tae-Young Chung ,  Ki-Nam Kim ,  Yoo-Sang Hwang

IPC分类号： H01L21338

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823456 ,  H01L29/41783 ,  H01L29/66537 ,  H01L29/66545

摘要： Self-aligned contacts in integrated circuits can be formed on an integrated circuit substrate having an active region. A groove can be formed in the insulating layer and a conductive material can be formed in the groove to a level that is recessed in the groove. An insulating material can be formed in the groove on the conductive material that has an etch selectivity with respect to the insulating layer. A contact that is self-aligned to the active region can be then be formed.

摘要翻译： 集成电路中的自对准触点可以形成在具有有源区的集成电路基板上。 可以在绝缘层中形成沟槽，并且可以在沟槽中形成导电材料到凹陷在凹槽中的水平。 绝缘材料可以形成在导电材料上的相对于绝缘层具有蚀刻选择性的凹槽中。 然后可以形成与活性区域自对准的接触。

公开(公告)号：US06277702B1

公开(公告)日：2001-08-21

申请号：US09502520

申请日：2000-02-14

申请人： Yoon-Soo Chun ,  Yoo-Sang Hwang ,  Tae-Young Chung

发明人： Yoon-Soo Chun ,  Yoo-Sang Hwang ,  Tae-Young Chung

IPC分类号： H01L2120

CPC分类号： H01L28/75 ,  H01L27/10852

摘要： A storage element of a stacked capacitor having a high dielectric film for a semiconductor device and a method of fabricating the same, the storage element having a storage node comprising a bottom polysilicon layer, a barrier metal layer, and a transition metal layer with sidewall spacers formed on the barrier metal layer. The barrier metal layer and sidewall spacers prevent the polysilicon layer from being oxidized. The polysilicon layer is formed to a thickness that determines the height of the storage node. The transition metal layer directly interfacing the high dielectric film is thinly formed to avoid slope etching thereof and thereby prevent electrical bridges or shorts between adjacent storage nodes.

摘要翻译： 具有用于半导体器件的高电介质膜的堆叠电容器的存储元件及其制造方法，所述存储元件具有存储节点，所述存储节点包括底部多晶硅层，阻挡金属层和具有侧壁间隔物的过渡金属层 形成在阻挡金属层上。 阻挡金属层和侧壁间隔物防止多晶硅层被氧化。 多晶硅层形成为确定存储节点的高度的厚度。 直接连接高电介质膜的过渡金属层被薄形成，以避免其斜坡蚀刻，从而防止相邻存储节点之间的电桥或短路。

公开(公告)号：US06288446B1

公开(公告)日：2001-09-11

申请号：US09790642

申请日：2001-02-23

申请人： Dong-Hwa Kwak ,  Yoo-Sang Hwang ,  Tae-Young Chung

发明人： Dong-Hwa Kwak ,  Yoo-Sang Hwang ,  Tae-Young Chung

IPC分类号： H01G706

摘要： A semiconductor device and a method for making a semiconductor device having a pillar-shaped capacitor storage node compatible with a high dielectric film, wherein the pillar shaped capacitor storage node includes a thick conductive metal layer that is easily etched and a thin conductive layer completely coating the thick conductive metal layer. The thin conductive layer protects the thick conductive metal layer during subsequent high dielectric deposition and annealing and various oxidation process.

公开(公告)号：US06218296B1

公开(公告)日：2001-04-17

申请号：US09346922

申请日：1999-07-02

申请人： Dong-Hwa Kwak ,  Yoo-Sang Hwang ,  Tae-Young Chung

发明人： Dong-Hwa Kwak ,  Yoo-Sang Hwang ,  Tae-Young Chung

IPC分类号： H01L2144

CPC分类号： H01L27/10852 ,  H01L28/82 ,  H01L28/90

摘要： A semiconductor device and a method for making a semiconductor device having a pillar-shaped capacitor storage node compatible with a high dielectric film, wherein the pillar-shaped capacitor storage node includes a thick conductive metal layer that is easily etched and a thin conductive layer completely coating the thick conductive metal layer. The thin conductive layer protects the thick conductive metal layer during subsequent high dielectric deposition and annealing and various oxidation process.

摘要翻译： 一种半导体器件和制造具有与高介电膜兼容的柱状电容器存储节点的半导体器件的方法，其中柱状电容器存储节点包括易于蚀刻的厚导电金属层和完全薄的导电层 涂覆厚的导电金属层。 薄导电层在随后的高介电沉积和退火和各种氧化过程期间保护厚的导电金属层。