公开(公告)号：US20130052787A1

公开(公告)日：2013-02-28

申请号：US13494328

申请日：2012-06-12

申请人： Kwang-wook Lee ,  Sang-jun Lee ,  In-seak Hwang ,  In-sang Jeon ,  Byoung-yong Gwak ,  Ho-kyun An

发明人： Kwang-wook Lee ,  Sang-jun Lee ,  In-seak Hwang ,  In-sang Jeon ,  Byoung-yong Gwak ,  Ho-kyun An

IPC分类号： H01L21/02 ,  H01L21/20

CPC分类号： H01L27/10852 ,  H01L21/76816 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L28/91

摘要： A method of manufacturing a semiconductor device includes forming a bit line on a substrate comprising an active region; forming an interlayer insulating layer covering the bit line on the substrate; forming a first hole at a location of the active region through the interlayer insulating layer; forming a dummy contact layer by filling the first hole; forming a mold layer on the interlayer insulating layer and the dummy contact layer; forming a second hole at a location of the dummy contact layer through the mold layer; removing the dummy contact layer in the first hole through the second hole; forming an epitaxial layer on a portion of the active region, which is exposed at a lower surface of the first hole; and forming a lower electrode on internal surfaces of the first hole and the second hole.

摘要翻译： 制造半导体器件的方法包括在包括有源区的衬底上形成位线; 形成覆盖所述基板上的所述位线的层间绝缘层; 在有源区的位置通过层间绝缘层形成第一孔; 通过填充第一孔形成虚拟接触层; 在层间绝缘层和虚拟接触层上形成模层; 在所述模拟接触层的位置处通过所述模制层形成第二孔; 通过第二孔去除第一孔中的虚拟接触层; 在所述有源区的在所述第一孔的下表面处露出的部分上形成外延层; 以及在所述第一孔和所述第二孔的内表面上形成下电极。

公开(公告)号：US20100093165A1

公开(公告)日：2010-04-15

申请号：US12453866

申请日：2009-05-26

申请人： Ki-ho Bae ,  Kwang-bok Kim ,  Choong-kee Seong ,  In-seak Hwang ,  Ki-jong Park ,  Kyung-hyun Kim

发明人： Ki-ho Bae ,  Kwang-bok Kim ,  Choong-kee Seong ,  In-seak Hwang ,  Ki-jong Park ,  Kyung-hyun Kim

IPC分类号： H01L21/8234 ,  H01L21/306

CPC分类号： H01L27/11519 ,  H01L21/0334 ,  H01L27/11521

摘要： Provided is a method of fabricating an integrated circuit semiconductor device. The method may include forming a plurality of gate patterns spaced apart from each other on a semiconductor substrate, the plurality of gate patterns including gate electrodes and gate capping patterns. After an interlayer insulating layer is formed to insulate the gate patterns, the interlayer insulating layer and the gate capping patterns may be planarized by etching until top surfaces of the gate electrodes are exposed. Gate metal silicide layers may be selectively formed on the gate electrodes.

摘要翻译： 提供一种制造集成电路半导体器件的方法。 所述方法可以包括在半导体衬底上形成彼此间隔开的多个栅极图案，所述多个栅极图案包括栅电极和栅极封盖图案。 在形成层间绝缘层以使栅极图案绝缘之后，可以通过蚀刻来平坦化层间绝缘层和栅极封盖图案，直到栅电极的顶表面露出。 可以在栅电极上选择性地形成栅极金属硅化物层。

公开(公告)号：US20080220375A1

公开(公告)日：2008-09-11

申请号：US12074430

申请日：2008-03-04

申请人： Kyoung-Chul Kim ,  Bong-Chan Kim ,  In-Seak Hwang ,  Kwang-Wook Lee

发明人： Kyoung-Chul Kim ,  Bong-Chan Kim ,  In-Seak Hwang ,  Kwang-Wook Lee

IPC分类号： G03F7/26 ,  G03F7/30

CPC分类号： G03F7/091 ,  G03F7/40 ,  G03F7/42

摘要： In a method of reworking a substrate, an organic anti-reflection coating (ARC) layer is formed on the substrate having an amorphous carbon pattern. A photoresist pattern is formed on the organic ARC layer. The photoresist pattern is entirely exposed when the photoresist pattern has a selected level of defects, and then the photoresist pattern is removed by a developing process. The substrate may be reworked without damaging the organic ARC layer, and the amorphous carbon pattern may include an alignment key and/or an overlay key.

摘要翻译： 在对衬底进行再加工的方法中，在具有无定形碳图案的衬底上形成有机抗反射涂层（ARC）层。 在有机ARC层上形成光刻胶图形。 当光致抗蚀剂图案具有选定的缺陷水平时，光致抗蚀剂图案完全曝光，然后通过显影过程去除光致抗蚀剂图案。 可以对衬底进行再加工而不损坏有机ARC层，并且非晶碳图案可以包括对准键和/或覆盖键。

公开(公告)号：US07405164B2

公开(公告)日：2008-07-29

申请号：US11488706

申请日：2006-07-19

申请人： In-Gi Kim ,  In-Seak Hwang ,  Dae-Hyuk Chung ,  Kyoung-Hwan Kim

发明人： In-Gi Kim ,  In-Seak Hwang ,  Dae-Hyuk Chung ,  Kyoung-Hwan Kim

IPC分类号： H01L21/302

CPC分类号： H01L21/31138 ,  G03F7/42 ,  H01J37/3244

摘要： In an apparatus and method for removing a photoresist structure from a substrate, a chamber for receiving the substrate includes a showerhead for uniformly distributing a mixture of water vapor and ozone gas onto the substrate. The showerhead includes a first space having walls and configured to receive the water vapor, and a second space connected to the first space so that the water vapor is supplied to and partially condensed into liquid water on one or more walls of the first space. Ozone gas and water vapor without liquid water may be supplied to the second space to form the mixture therein. The showerhead may be heated to vaporize the liquid water on a given surface of the first space.

公开(公告)号：US20070138126A1

公开(公告)日：2007-06-21

申请号：US11604825

申请日：2006-11-28

申请人： Keum-Joo Lee ,  In-Seak Hwang ,  Jong-Won Kim

发明人： Keum-Joo Lee ,  In-Seak Hwang ,  Jong-Won Kim

IPC分类号： H01B13/00 ,  B44C1/22 ,  C03C25/68 ,  C03C15/00

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： Example embodiments relate to a method of forming a conductive structure. Other example embodiments relate to a method of forming a conductive structure capable of storing or transmitting electric charges. In example embodiments, when a conductive structure including first and second conductive patterns extending in a first horizontal direction is formed, at least one of the first and second conductive patterns may decreases in size. When the conductive structure is vertically bisected in a second horizontal direction perpendicular to the first horizontal direction to form conductive members, a coupling effect generated between the conductive members adjacent to each other may be reduced.

摘要翻译： 示例性实施例涉及形成导电结构的方法。 其他示例性实施例涉及形成能够存储或传输电荷的导电结构的方法。 在示例性实施例中，当形成包括在第一水平方向上延伸的第一和第二导电图案的导电结构时，第一和第二导电图案中的至少一个尺寸可能减小。 当导电结构在与第一水平方向垂直的第二水平方向上垂直平分以形成导电构件时，可以减少彼此相邻的导电构件之间产生的耦合效应。

公开(公告)号：US20070020943A1

公开(公告)日：2007-01-25

申请号：US11488706

申请日：2006-07-19

申请人： In-Gi Kim ,  In-Seak Hwang ,  Dae-Hyuk Chung ,  Kyoung-Hwan Kim

发明人： In-Gi Kim ,  In-Seak Hwang ,  Dae-Hyuk Chung ,  Kyoung-Hwan Kim

IPC分类号： H01L21/306 ,  H01L21/302

CPC分类号： H01L21/31138 ,  G03F7/42 ,  H01J37/3244

摘要： In an apparatus and method for removing a photoresist structure from a substrate, a chamber for receiving the substrate includes a showerhead for uniformly distributing a mixture of water vapor and ozone gas onto the substrate. The showerhead includes a first space having walls and configured to receive the water vapor, and a second space connected to the first space so that the water vapor is supplied to and partially condensed into liquid water on one or more walls of the first space. Ozone gas and water vapor without liquid water may be supplied to the second space to form the mixture therein. The showerhead may be heated to vaporize the liquid water on a given surface of the first space.

摘要翻译： 在用于从基板去除光致抗蚀剂结构的装置和方法中，用于接收基板的室包括用于将水蒸气和臭氧气体的混合物均匀分布到基板上的喷头。 喷头包括具有壁并构造成接收水蒸气的第一空间，以及连接到第一空间的第二空间，使得水蒸汽被供应到第一空间的一个或多个壁上并部分地冷凝成液态水。 臭氧气体和没有液态水的水蒸汽可以供应到第二空间以在其中形成混合物。 可以加热喷头以蒸发第一空间的给定表面上的液态水。

公开(公告)号：US20060287208A1

公开(公告)日：2006-12-21

申请号：US11467736

申请日：2006-08-28

申请人： Kwang-Wook Lee ,  In-Seak Hwang ,  Keum-Joo Lee ,  Chang-Lyong Song ,  Yong-Sun Ko ,  Kui-Jong Baek ,  Woong Han

发明人： Kwang-Wook Lee ,  In-Seak Hwang ,  Keum-Joo Lee ,  Chang-Lyong Song ,  Yong-Sun Ko ,  Kui-Jong Baek ,  Woong Han

IPC分类号： C11D7/32

CPC分类号： H01L21/02071 ,  C11D3/0084 ,  C11D7/3281 ,  C11D11/0047 ,  C23G1/106

摘要： A corrosion-inhibiting cleaning composition for semiconductor wafer processing includes hydrogen peroxide at a concentration in a range from about 0.5 wt % to about 5 wt %, sulfuric acid at a concentration in a range from about 1 wt % to about 10 wt %, hydrogen fluoride at a concentration in a range from about 0.01 wt % to about 1 wt %; an azole at a concentration in a range from about 0.1 wt % to about 5 wt % and deionized water. The azole operates to inhibit corrosion of a metal layer being cleaned by chelating with a surface of the metal layer during a cleaning process.

摘要翻译： 用于半导体晶片处理的腐蚀抑制清洁组合物包括浓度在约0.5重量％至约5重量％范围内的浓度在约1重量％至约10重量％范围内的硫酸，氢气 浓度在约0.01重量％至约1重量％范围内的氟化物; 浓度在约0.1重量％至约5重量％范围内的唑类和去离子水。 在清洁过程中，唑类用于通过与金属层的表面螯合来抑制被清洁的金属层的腐蚀。

公开(公告)号：US20060270241A1

公开(公告)日：2006-11-30

申请号：US11420943

申请日：2006-05-30

申请人： Kyoung-Chul Kim ,  Dae-Keun Kang ,  Se-Ho Cha ,  In-Seak Hwang ,  Keum-Joo Lee

发明人： Kyoung-Chul Kim ,  Dae-Keun Kang ,  Se-Ho Cha ,  In-Seak Hwang ,  Keum-Joo Lee

IPC分类号： B08B3/00 ,  C23G1/00 ,  H01L21/302

CPC分类号： H01L21/31138 ,  B08B7/00 ,  B08B7/0035 ,  G03F7/427 ,  H01L28/91

摘要： In a method of removing a photoresist pattern from a substrate without deteriorating a lower electrode or increasing processing time, ozone gas may be provided onto a substrate on which a photoresist pattern may be formed. An oxidation-decomposition process may be carried out using the ozone gas, to thereby decompose the photoresist pattern on the substrate. The decomposed photoresist pattern may be dissolved into water and removed from the substrate in a rinsing process. Accordingly, a photoresist pattern in an opening having a relatively high aspect ratio may be sufficiently removed from a substrate without deteriorating the lower electrode or increasing processing time.

摘要翻译： 在不损坏下电极或增加处理时间的情况下从基板上除去光致抗蚀剂图案的方法中，可以在可以形成光致抗蚀剂图案的基板上提供臭氧气体。 可以使用臭氧气体进行氧化分解处理，从而分解基板上的光致抗蚀剂图案。 分解的光致抗蚀剂图案可以在漂洗过程中溶解在水中并从基材中除去。 因此，具有相对高的纵横比的开口中的光致抗蚀剂图案可以从基板充分地去除而不会使下电极恶化或增加处理时间。

公开(公告)号：US06838330B2

公开(公告)日：2005-01-04

申请号：US10445843

申请日：2003-05-28

申请人： Bong-Ho Moon ,  Ju-Yun Cheol ,  Yong-Sun Ko ,  In-Seak Hwang

发明人： Bong-Ho Moon ,  Ju-Yun Cheol ,  Yong-Sun Ko ,  In-Seak Hwang

IPC分类号： H01L21/768 ,  H01L21/60 ,  H01L21/8238

CPC分类号： H01L21/02063 ,  H01L21/76897

摘要： A method of forming a contact hole of a semiconductor device that is able to prevent excessive etching of an interlayer dielectric pattern includes forming a gate pattern including a first insulation layer pattern, a conductive layer pattern, a capping insulation layer pattern, and a second insulation layer pattern on a substrate; forming a spacer using an insulating material on a sidewall of the gate pattern; forming an interlayer dielectric on the substrate on which the gate pattern and the spacer are formed; forming a contact hole and an interlayer dielectric pattern for exposing the substrate by etching the interlayer dielectric; forming a liner spacer on a sidewall of the spacer and the interlayer dielectric pattern; and cleaning the resultant structure using a cleaning solution. The cleaning solution preferably includes includes ozone water and hydrogen fluoride (HF).

摘要翻译： 形成能够防止层间电介质图案的过度蚀刻的半导体器件的接触孔的方法包括形成包括第一绝缘层图案，导电层图案，封盖绝缘层图案和第二绝缘体的栅极图案 层图案; 在所述栅极图案的侧壁上使用绝缘材料形成间隔物; 在其上形成有栅极图案和间隔物的基板上形成层间电介质; 形成用于通过蚀刻所述层间电介质来暴露所述衬底的接触孔和层间电介质图案; 在间隔物的侧壁和层间介质图案上形成衬垫; 并使用清洁溶液清洗所得到的结构。 清洗液最好包括臭氧水和氟化氢（HF）。

公开(公告)号：US06331478B1

公开(公告)日：2001-12-18

申请号：US09685456

申请日：2000-10-09

申请人： Keum-joo Lee ,  In-seak Hwang ,  Yong-sun Ko ,  Chang-Iyoung Song

发明人： Keum-joo Lee ,  In-seak Hwang ,  Yong-sun Ko ,  Chang-Iyoung Song

IPC分类号： H01L214763

CPC分类号： H01L29/42376 ,  H01L21/28061 ,  H01L21/28114 ,  H01L21/32134 ,  H01L21/32139 ,  H01L21/76897 ,  H01L27/10873

摘要： Methods for manufacturing a semiconductor device, in which a chamfered metal silicide layer is formed by a 2-stage continuous wet etching process using different etchants, thereby resulting in a sufficient insulation margin between a lower conductive layer including the metal silicide layer and the contact plug self-aligned with the lower conductive layer are disclosed. In the manufacture of a semiconductor device, a mask pattern is formed on a metal silicide layer to expose a portion of the metal silicide layer. The exposed portion of the metal silicide layer is isotropically etched in a first etchant to form a metal silicide layer with a shallow groove, and defects due to the silicon remaining on the surface of the metal silicide layer with the shallow groove are removed using a second etchant, to form a metal silicide layer with a smooth surface. Microelectronic structures produced by methods of the present invention are also disclosed.

摘要翻译： 制造半导体器件的方法，其中通过使用不同蚀刻剂的2阶段连续湿蚀刻工艺形成倒角金属硅化物层，从而在包括金属硅化物层的下导电层和接触插塞之间形成足够的绝缘边缘 公开了与下导电层自对准。 在半导体器件的制造中，在金属硅化物层上形成掩模图案以暴露金属硅化物层的一部分。 金属硅化物层的暴露部分在第一蚀刻剂中被各向同性地蚀刻以形成具有浅槽的金属硅化物层，并且由于在具有浅槽的金属硅化物层的表面上残留的硅的缺陷被使用第二 蚀刻剂，以形成具有光滑表面的金属硅化物层。 还公开了通过本发明的方法生产的微电子结构。