公开(公告)号：US08526228B2

公开(公告)日：2013-09-03

申请号：US13345636

申请日：2012-01-06

申请人： Leland Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

发明人： Leland Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC分类号： G11C11/36 ,  G11C16/24

CPC分类号： G11C16/24 ,  G11C11/412 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1116

摘要： An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration for storing a single data bit; first and second pass-gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass-gate transistors coupled to a write bit line through a series outer diode between the pass-gate and the write bit line oriented to block charge transfer from the write bit line into the cell; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. The 8-transistor SRAM cell is adapted to prevent the value of the bit stored in the cell from changing state.

摘要翻译： 一个8晶体管SRAM单元，包括两个上拉晶体管和两个交叉耦合的反相器配置中的下拉晶体管，用于存储单个数据位; 第一和第二栅极晶体管具有耦合到写入字线的栅极端子和耦合到通过栅极和写入位之间的串联外部二极管的写入位线的每个通过栅极晶体管的源极或漏极 线路阻止从写入位线进入电池的电荷转移; 以及耦合到所述两个上拉和两个下拉晶体管的第一和第二读取晶体管，所述读取晶体管中的一个具有耦合到读取字线的栅极端子和耦合到读取位线的源极或漏极。 8晶体管SRAM单元适于防止存储在单元中的位的值改变状态。

公开(公告)号：US08367485B2

公开(公告)日：2013-02-05

申请号：US12551941

申请日：2009-09-01

申请人： Leland Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

发明人： Leland Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC分类号： H01L21/84

CPC分类号： H01L27/1203 ,  H01L21/8238 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78621

摘要： A method for fabricating a semiconductor device includes forming a gate stack on an active region of a silicon-on-insulator substrate. The active region is within a semiconductor layer and is doped with an p-type dopant. A gate spacer is formed surrounding the gate stack. A first trench is formed in a region reserved for a source region and a second trench is formed in a region reserved for a drain region. The first and second trenches are formed while maintaining exposed the region reserved for the source region and the region reserved for the drain region. Silicon germanium is epitaxially grown within the first trench and the second trench while maintaining exposed the regions reserved for the source and drain regions, respectively.

摘要翻译： 一种用于制造半导体器件的方法包括在绝缘体上硅衬底的有源区上形成栅叠层。 有源区在半导体层内并掺杂有p型掺杂剂。 围绕栅极堆叠形成栅极间隔物。 在为源极区域保留的区域中形成第一沟槽，并且在为漏极区域保留的区域中形成第二沟槽。 形成第一和第二沟槽，同时保持暴露为源极区域保留的区域和为漏极区域保留的区域。 硅锗外延生长在第一沟槽和第二沟槽内，同时保持分别保留用于源区和漏区的区域。

公开(公告)号：US08174074B2

公开(公告)日：2012-05-08

申请号：US12551804

申请日：2009-09-01

申请人： Chung-Hsun Lin ,  Isaac Lauer ,  Jeffrey W. Sleight

发明人： Chung-Hsun Lin ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC分类号： H01L27/12

CPC分类号： H01L29/78687 ,  H01L21/26586 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66742 ,  H01L29/7835 ,  H01L29/78612 ,  H01L29/78624

摘要： A semiconductor device, an integrated circuit, and method for fabricating the same are disclosed. The semiconductor device includes a gate stack formed on an active region of a silicon-on-insulator substrate. A gate spacer is formed over the gate stack. A source region that includes embedded silicon germanium is formed within the semiconductor layer. A drain region that includes embedded silicon germanium is formed within the semiconductor layer. The source region includes an angled implantation region that extends into the embedded silicon germanium of the source region, and is asymmetric relative to the drain region.

摘要翻译： 公开了一种半导体器件，集成电路及其制造方法。 半导体器件包括形成在绝缘体上硅衬底的有源区上的栅叠层。 在栅极堆叠上形成栅极间隔物。 在半导体层内形成包括嵌入硅锗的源区。 在半导体层内形成包括嵌入硅锗的漏区。 源极区域包括延伸到源极区域的嵌入式硅锗中的成角度的注入区域，并且相对于漏极区域是不对称的。

公开(公告)号：US20110049627A1

公开(公告)日：2011-03-03

申请号：US12551941

申请日：2009-09-01

申请人： LELAND CHANG ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

发明人： LELAND CHANG ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L27/1203 ,  H01L21/8238 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78621

摘要： A method for fabricating a semiconductor device includes forming a gate stack on an active region of a silicon-on-insulator substrate. The active region is within a semiconductor layer and is doped with an p-type dopant. A gate spacer is formed surrounding the gate stack. A first trench is formed in a region reserved for a source region and a second trench is formed in a region reserved for a drain region. The first and second trenches are formed while maintaining exposed the region reserved for the source region and the region reserved for the drain region. Silicon germanium is epitaxially grown within the first trench and the second trench while maintaining exposed the regions reserved for the source and drain regions, respectively.

摘要翻译： 一种制造半导体器件的方法包括在绝缘体上硅衬底的有源区上形成栅叠层。 有源区在半导体层内并掺杂有p型掺杂剂。 围绕栅极堆叠形成栅极间隔物。 在为源极区域保留的区域中形成第一沟槽，并且在为漏极区域保留的区域中形成第二沟槽。 形成第一和第二沟槽，同时保持暴露为源极区域保留的区域和为漏极区域保留的区域。 硅锗外延生长在第一沟槽和第二沟槽内，同时保持分别保留用于源区和漏区的区域。

公开(公告)号：US08531871B2

公开(公告)日：2013-09-10

申请号：US13345619

申请日：2012-01-06

申请人： Leland Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

发明人： Leland Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC分类号： G11C11/00 ,  G11C11/417

CPC分类号： G11C11/417 ,  G11C11/412

摘要： An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration to form two inverters for storing a single data bit, wherein each of the inverters includes a Schottky diode; first and second pass gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass gate transistors coupled to a write bit line; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. In a preferred embodiment, the 8-transistor SRAM cell has column select writing enabled for writing a value to the 8-transistor SRAM cell without inadvertently also writing a value to another 8-transistor SRAM cell.

摘要翻译： 一种8晶体管SRAM单元，其包括两个上拉晶体管和两个交叉耦合的反相器配置的下拉晶体管，以形成用于存储单个数据位的两个反相器，其中每个反相器包括肖特基二极管; 第一和第二栅极晶体管，其具有耦合到写入字线的栅极端子和耦合到写位线的每个通路栅极晶体管的源极或漏极; 以及耦合到所述两个上拉和两个下拉晶体管的第一和第二读取晶体管，所述读取晶体管中的一个具有耦合到读取字线的栅极端子和耦合到读取位线的源极或漏极。 在优选实施例中，8晶体管SRAM单元具有使能用于向8晶体管SRAM单元写入值的列选择写入，而无需另外向另一个8-晶体管SRAM单元写入一个值。

公开(公告)号：US20130176770A1

公开(公告)日：2013-07-11

申请号：US13345629

申请日：2012-01-06

申请人： Leland Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

发明人： Leland Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC分类号： G11C11/40

CPC分类号： G11C11/412

摘要： An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration for storing a single data bit; first and second pass-gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass-gate transistors coupled to a write bit line; inner junction diodes at shared source/drain terminals of the pass-gate and pull-down transistors oriented to block charge transfer from the write bit line into the cell; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. The 8-transistor SRAM cell is adapted to prevent the value of the bit stored in the cell from changing state.

摘要翻译： 一个8晶体管SRAM单元，包括两个上拉晶体管和两个交叉耦合的反相器配置的下拉晶体管，用于存储单个数据位; 第一和第二栅极晶体管具有耦合到写入字线的栅极端子和耦合到写入位线的每个通过栅极晶体管的源极或漏极; 导通栅极和下拉晶体管的共用源极/漏极端子处的内部结二极管，用于阻止从写位线到电池的电荷转移; 以及耦合到所述两个上拉和两个下拉晶体管的第一和第二读取晶体管，所述读取晶体管中的一个具有耦合到读取字线的栅极端子和耦合到读取位线的源极或漏极。 8晶体管SRAM单元适于防止存储在单元中的位的值改变状态。

公开(公告)号：US20110049626A1

公开(公告)日：2011-03-03

申请号：US12551804

申请日：2009-09-01

申请人： CHUNG-HSUN LIN ,  Isaac Lauer ,  Jeffrey W. Sleight

发明人： CHUNG-HSUN LIN ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/78687 ,  H01L21/26586 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66742 ,  H01L29/7835 ,  H01L29/78612 ,  H01L29/78624

摘要： A semiconductor device, an integrated circuit, and method for fabricating the same are disclosed. The semiconductor device includes a gate stack formed on an active region of a silicon-on-insulator substrate. A gate spacer is formed over the gate stack. A source region that includes embedded silicon germanium is formed within the semiconductor layer. A drain region that includes embedded silicon germanium is formed within the semiconductor layer. The source region includes an angled implantation region that extends into the embedded silicon germanium of the source region, and is asymmetric relative to the drain region.

摘要翻译： 公开了一种半导体器件，集成电路及其制造方法。 半导体器件包括形成在绝缘体上硅衬底的有源区上的栅叠层。 在栅极堆叠上形成栅极间隔物。 在半导体层内形成包括嵌入硅锗的源区。 在半导体层内形成包括嵌入硅锗的漏区。 源极区域包括延伸到源极区域的嵌入式硅锗中的成角度的注入区域，并且相对于漏极区域是不对称的。

公开(公告)号：US20110133169A1

公开(公告)日：2011-06-09

申请号：US12630942

申请日：2009-12-04

申请人： Sarunya Bangsaruntip ,  Josephine B. Chang ,  Isaac Lauer ,  Jeffrey W. Sleight

发明人： Sarunya Bangsaruntip ,  Josephine B. Chang ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC分类号： H01L29/12 ,  H01L21/336 ,  H01L29/78 ,  H01L29/08

CPC分类号： H01L29/42392 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/78696

摘要： A method for forming a nanowire tunnel field effect transistor (FET) device includes forming a nanowire suspended by first and second pad regions over a semiconductor substrate, the nanowire including a core portion and a dielectric layer, forming a gate structure around a portion of the dielectric layer, forming a first spacer around portions of the nanowire extending from the gate structure, implanting ions in a first portion of the nanowire, implanting ions in the dielectric layer of a second portion of the nanowire, removing the dielectric layer from the second portion of the nanowire, removing the core portion of the second portion of the exposed nanowire to form a cavity, and epitaxially growing a doped semiconductor material in the cavity from exposed cross sections of the nanowire and the second pad region to connect the exposed cross sections of the nanowire to the second pad region.

摘要翻译： 一种形成纳米线隧道场效应晶体管（FET）器件的方法包括：在半导体衬底上形成由第一和第二衬垫区域悬挂的纳米线，纳米线包括芯部分和电介质层，在该部分的一部分周围形成栅极结构 电介质层，在从所述栅极结构延伸的所述纳米线的一部分周围形成第一间隔物，在所述纳米线的第一部分中注入离子，将所述离子注入到所述纳米线的第二部分的介电层中，从所述第二部分去除所述电介质层 去除所述暴露的纳米线的第二部分的核心部分以形成空腔，并且从所述纳米线和所述第二焊盘区域的暴露的横截面外延生长所述空腔中的掺杂半导体材料，以将所述暴露的横截面 纳米线到第二垫区域。

公开(公告)号：US20140073106A1

公开(公告)日：2014-03-13

申请号：US13610961

申请日：2012-09-12

申请人： Josephine B. Chang ,  Gen Pei Lauer ,  Isaac Lauer ,  Jeffrey W. Sleight

发明人： Josephine B. Chang ,  Gen Pei Lauer ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC分类号： H01L21/331

CPC分类号： H01L29/66265 ,  H01L21/84 ,  H01L29/6625 ,  H01L29/7317

摘要： A method of forming a lateral bipolar transistor. The method includes forming a silicon on insulator (SOI) substrate having a bottom substrate layer, a buried oxide layer (BOX) on top of the substrate layer, and a silicon on insulator (SOI) layer on top of the BOX layer, forming a dummy gate and spacer on top of the silicon on insulator layer, doping the SOI layer with positive or negative ions, depositing an inter layer dielectric (ILD), using chemical mechanical planarization (CMP) to planarize the ILD, removing the dummy gate creating a gate trench which reveals the base of the dummy gate, doping the dummy gate base, depositing a layer of polysilicon on top of the SOI layer and into the gate trench, etching the layer of polysilicon so that it only covers the dummy gate base, and applying a self-aligned silicide process.

摘要翻译： 一种形成横向双极晶体管的方法。 该方法包括形成具有底部衬底层的绝缘体上硅（SOI）衬底，在衬底层顶部上的掩埋氧化物层（BOX）以及BOX层顶部上的绝缘体上硅（SOI）层，形成 在绝缘体上硅层的顶部设置虚拟栅极和间隔物，用正离子或负离子掺杂SOI层，使用化学机械平面化（CMP）沉积层间电介质（ILD）以平坦化ILD，去除伪栅极，从而形成 栅极沟槽，其显示虚拟栅极的基极，掺杂伪栅极基底，在SOI层的顶部上沉积多晶硅层并进入栅极沟槽，蚀刻多晶硅层，使得其仅覆盖伪栅极基极，以及 应用自对准硅化物工艺。

公开(公告)号：US20130221319A1

公开(公告)日：2013-08-29

申请号：US13405682

申请日：2012-02-27

申请人： Jeffrey W. Sleight ,  Josephine B. Chang ,  Isaac Lauer ,  Shreesh Narasimha

发明人： Jeffrey W. Sleight ,  Josephine B. Chang ,  Isaac Lauer ,  Shreesh Narasimha

IPC分类号： H01L29/775 ,  H01L21/335

CPC分类号： H01L29/66477 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

摘要： Non-planar semiconductor devices are provided that include at least one semiconductor nanowire suspended above a semiconductor oxide layer that is present on a first portion of a bulk semiconductor substrate. An end segment of the at least one semiconductor nanowire is attached to a first semiconductor pad region and another end segment of the at least one semiconductor nanowire is attached to a second semiconductor pad region. The first and second pad regions are located above and are in direct contact with a second portion of the bulk semiconductor substrate which is vertically offsets from the first portion. The structure further includes a gate surrounding a central portion of the at least one semiconductor nanowire, a source region located on a first side of the gate, and a drain region located on a second side of the gate which is opposite the first side of the gate.

摘要翻译： 提供非平面半导体器件，其包括悬浮在存在于体半导体衬底的第一部分上的半导体氧化物层上的至少一个半导体纳米线。 所述至少一个半导体纳米线的端部段附接到第一半导体焊盘区域，并且所述至少一个半导体纳米线的另一个端部段附接到第二半导体焊盘区域。 第一和第二焊盘区域位于与第一部分垂直偏移的体半导体衬底的第二部分的上方并直接接触。 所述结构还包括围绕所述至少一个半导体纳米线的中心部分的栅极，位于所述栅极的第一侧上的源极区域和位于所述栅极的与所述栅极的第一侧相对的第二侧上的漏极区域 门。