公开(公告)号：US20120286329A1

公开(公告)日：2012-11-15

申请号：US13106900

申请日：2011-05-13

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

IPC分类号： H01L29/06 ,  H01L21/336

CPC分类号： H01L29/66772 ,  H01L29/7848 ,  H01L29/78654

摘要： A method and a structure are disclosed relating to strained body UTSOI FET devices. The method includes forming voids in the source/drain regions that penetrate down into the substrate below the insulating layer. The voids are epitaxially filled with a semiconductor material of a differing lattice constant than the one of the SOI layer, thus becoming a stressor block, and imparts a strain onto the FET device body.

摘要翻译： 公开了与应变体UTSOI FET器件有关的方法和结构。 该方法包括在源极/漏极区域中形成穿透绝缘层下方的衬底中的空隙。 空隙被外延填充有与SOI层不同的晶格常数的半导体材料，因此成为应力块，并且在FET器件本体上施加应变。

公开(公告)号：US20120276695A1

公开(公告)日：2012-11-01

申请号：US13098352

申请日：2011-04-29

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

IPC分类号： H01L21/8238

CPC分类号： H01L27/1211 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845

摘要： A method is disclosed which is characterized as being process integration of raised source/drain and strained body for ultra thin planar and FinFET CMOS devices. NFET and PFET devices have their source/drain raised by selective epitaxy with in-situ p-type doped SiGe for the PFET device, and in-situ n-type doped Si:C for the NFET device. Such raised source/drains offer low parasitic resistance and they impart a strain onto the device bodies of the correct sign for respective carrier, electron or hole, mobility enhancement.

摘要翻译： 公开了一种方法，其特征在于用于超薄平面和FinFET CMOS器件的凸起源极/漏极和应变体的处理集成。 NFET和PFET器件通过用于PFET器件的原位p型掺杂SiGe的选择性外延以及用于NFET器件的原位n型掺杂Si：C来提高其源极/漏极。 这种升高的源极/漏极提供低的寄生电阻，并且它们对于相应的载流子，电子或空穴，迁移率增强赋予了正确符号的器件体上的应变。

公开(公告)号：US20120267722A1

公开(公告)日：2012-10-25

申请号：US13540801

申请日：2012-07-03

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

IPC分类号： H01L27/088

CPC分类号： H01L21/823431 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/785

摘要： An FET device structure has a Fin-FET device with a fin of a Si based material. An oxide element is abutting the fin and exerts pressure onto the fin. The Fin-FET device channel is compressively stressed due to the pressure on the fin. A further FET device structure has Fin-FET devices in a row. An oxide element extending perpendicularly to the row of fins is abutting the fins and exerts pressure onto the fins. Device channels of the Fin-FET devices are compressively stressed due to the pressure on the fins.

摘要翻译： FET器件结构具有具有Si基材料的翅片的Fin-FET器件。 氧化物元件邻接翅片并对翅片施加压力。 Fin-FET器件通道由于鳍上的压力而受到压缩应力。 另外的FET器件结构具有Fin-FET器件。 垂直于翅片排延伸的氧化物元件邻接散热片并对翅片施加压力。 Fin-FET器件的器件通道由于鳍片上的压力而受到压缩应力。

公开(公告)号：US08169025B2

公开(公告)日：2012-05-01

申请号：US12689339

申请日：2010-01-19

申请人： Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L27/12

CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L29/7849

摘要： A semiconductor device and fabrication method include a strained semiconductor layer having a strain in one axis. A long fin and a short fin are formed in the semiconductor layer such that the long fin has a strained length along the one axis. An n-type transistor is formed on the long fin, and a p-type transistor is formed on the at least one short fin. The strain in the n-type transistor improves performance.

摘要翻译： 半导体器件和制造方法包括在一个轴上具有应变的应变半导体层。 在半导体层中形成长鳍片和短鳍片，使得长鳍片沿着一个轴线具有应变长度。 在长鳍片上形成n型晶体管，在该至少一个短鳍片上形成p型晶体管。 n型晶体管中的应变提高了性能。

公开(公告)号：US20110284967A1

公开(公告)日：2011-11-24

申请号：US12786397

申请日：2010-05-24

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L29/7843 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

摘要： A method for fabricating an FET device is disclosed. The method includes Fin-FET devices with fins that are composed of a first material, and then merged together by epitaxial deposition of a second material. The fins are vertically recesses using a selective etch. A continuous silicide layer is formed over the increased surface areas of the first material and the second material, leading to smaller resistance. A stress liner overlaying the FET device is afterwards deposited. An FET device is also disclosed, which FET device includes a plurality of Fin-FET devices, the fins of which are composed of a first material. The FET device includes a second material, which is epitaxially merging the fins. The fins are vertically recessed relative to an upper surface of the second material. The FET device furthermore includes a continuous silicide layer formed over the fins and over the second material, and a stress liner covering the device.

摘要翻译： 公开了一种用于制造FET器件的方法。 该方法包括具有由第一材料构成的翅片的Fin-FET器件，然后通过外延沉积第二材料而合并在一起。 翅片是使用选择性蚀刻的垂直凹部。 在第一材料和第二材料的增加的表面积上形成连续的硅化物层，导致较小的电阻。 覆盖FET器件的应力衬垫之后被沉积。 还公开了一种FET器件，该FET器件包括多个Fin-FET器件，其翅片由第一材料构成。 FET器件包括第二材料，其外延地融合鳍片。 翅片相对于第二材料的上表面垂直凹入。 FET器件还包括形成在鳍片上方和第二材料上的连续硅化物层，以及覆盖该器件的应力衬垫。

公开(公告)号：US08304301B2

公开(公告)日：2012-11-06

申请号：US12621299

申请日：2009-11-18

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Dechao Guo ,  Pranita Kulkarni ,  Philip J. Oldiges ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Dechao Guo ,  Pranita Kulkarni ,  Philip J. Oldiges ,  Ghavam G. Shahidi

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L29/66636 ,  H01L29/66772 ,  H01L29/78621 ,  H01L29/78654

摘要： A semiconductor device and a method of fabricating a semiconductor device are disclosed. In one embodiment, the method comprises providing a semiconductor substrate, epitaxially growing a Ge layer on the substrate, and epitaxially growing a semiconductor layer on the Ge layer, where the semiconductor layer has a thickness of 10 nm or less. This method further comprises removing at least a portion of the Ge layer to form a void beneath the Si layer, and filling the void at least partially with a dielectric material. In this way, the semiconductor layer becomes an extremely thin semiconductor-on-insulator layer. In one embodiment, after the void is filled with the dielectric material, in-situ doped source and drain regions are grown on the semiconductor layer. In one embodiment, the method further comprises annealing said source and drain regions to form doped extension regions in the semiconductor layer. Epitaxially growing the extremely thin semiconductor layer on the Ge layer ensures good thickness control across the wafer. This process could be used for SOI or bulk wafers.

摘要翻译： 公开了半导体器件和制造半导体器件的方法。 在一个实施例中，该方法包括提供半导体衬底，在衬底上外延生长Ge层，并在Ge层上外延生长半导体层，其中半导体层的厚度为10nm或更小。 该方法还包括去除Ge层的至少一部分以在Si层下形成空隙，并且至少部分地用电介质材料填充空隙。 以这种方式，半导体层成为非常薄的绝缘体上半导体层。 在一个实施例中，在空隙填充有电介质材料之后，在半导体层上生长原位掺杂的源极和漏极区。 在一个实施例中，该方法还包括退火所述源区和漏区以在半导体层中形成掺杂的延伸区。 在Ge层上外延生长极薄的半导体层确保跨晶片的良好的厚度控制。 该工艺可用于SOI或体晶片。

公开(公告)号：US08008138B2

公开(公告)日：2011-08-30

申请号：US12627424

申请日：2009-11-30

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ghavam G. Shahidi

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L29/78648 ,  H01L21/76251 ,  H01L21/84 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78687

摘要： A method of fabricating a semiconductor device is provided in which the channel of the device is present in an extremely thin semiconductor-on-insulator (ETSOI) layer, i.e., a semiconductor layer having a thickness of less than 20 nm. In one embodiment, the method begins with forming a first semiconductor layer and epitaxially growing a second semiconductor layer on a handling substrate. A first gate structure is formed on a first surface of the second semiconductor layer and source regions and drain regions are formed adjacent to the gate structure. The handling substrate and the first semiconductor layer are removed to expose a second surface of the second semiconductor layer that is opposite the first surface of the semiconductor layer. A second gate structure or a dielectric region is formed in contact with the second surface of the second semiconductor layer.

摘要翻译： 提供一种制造半导体器件的方法，其中器件的沟道存在于极薄的绝缘体上半导体（ETSOI）层，即厚度小于20nm的半导体层中。 在一个实施例中，该方法开始于形成第一半导体层并且在处理衬底上外延生长第二半导体层。 第一栅极结构形成在第二半导体层的第一表面上，并且源极区和漏极区被形成为与栅极结构相邻。 去除处理基板和第一半导体层以露出与半导体层的第一表面相对的第二半导体层的第二表面。 形成与第二半导体层的第二表面接触的第二栅极结构或电介质区域。

公开(公告)号：US20110037125A1

公开(公告)日：2011-02-17

申请号：US12542179

申请日：2009-08-17

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ghavam G. Shahidi

IPC分类号： H01L27/12 ,  H01L21/22 ,  H01L21/86

CPC分类号： H01L21/84 ,  H01L21/823814 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

摘要： A method of fabricating an electronic structure is provided that includes forming a first conductivity doped first semiconductor material on the SOI semiconductor layer of a substrate. The SOI semiconductor layer has a thickness of less than 10 nm. The first conductivity in-situ doped first semiconductor material is removed from a first portion of the SOI semiconductor layer, wherein a remaining portion of the first conductivity in-situ doped first semiconductor material is present on a second portion of SOI semiconductor layer. A second conductivity in-situ doped second semiconductor material is formed on the first portion of the SOI semiconductor layer, wherein a mask prohibits the second conductivity in-situ doped semiconductor material from being formed on the second portion of the SOI semiconductor layer. The dopants from the first and second conductivity in-situ doped semiconductor materials are diffused into the first semiconductor layer to form dopant regions.

摘要翻译： 提供一种制造电子结构的方法，其包括在衬底的SOI半导体层上形成第一导电掺杂的第一半导体材料。 SOI半导体层的厚度小于10nm。 第一导电性原位掺杂的第一半导体材料从SOI半导体层的第一部分去除，其中第一导电性原位掺杂的第一半导体材料的剩余部分存在于SOI半导体层的第二部分上。 第二导电性原位掺杂的第二半导体材料形成在SOI半导体层的第一部分上，其中掩模禁止在SOI半导体层的第二部分上形成第二导电性原位掺杂半导体材料。 来自第一和第二导电性原位掺杂半导体材料的掺杂剂扩散到第一半导体层中以形成掺杂区域。

公开(公告)号：US08138543B2

公开(公告)日：2012-03-20

申请号：US12621460

申请日：2009-11-18

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ghavam G. Shahidi

IPC分类号： H01L27/01

CPC分类号： H01L21/845 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1211 ,  H01L29/785

摘要： A circuit structure is disclosed which contains least one each of three different kinds of devices in a silicon layer on insulator (SOI): a planar NFET device, a planar PFET device, and a FinFET device. A trench isolation surrounds the planar NFET device and the planar PFET device penetrating through the SOI and abutting the insulator. Each of the three different kinds of devices contain a high-k gate dielectric layer and a mid-gap gate metal layer, each containing an identical high-k material and an identical mid-gap metal. Each of the three different kinds of devices have an individually optimized threshold value. A method for fabricating a circuit structure is also disclosed, which method involves defining portions in SOI respectively for three different kinds of devices: for a planar NFET device, for a planar PFET device, and for a FinFET device. The method also includes depositing in common a high-k gate dielectric layer and a mid-gap gate metal layer, and using workfunction modifying layers to individually adjust thresholds for the various kinds of devices.

摘要翻译： 公开了一种电路结构，其包含绝缘体上硅层（SOI）中的三种不同类型的器件中的至少一种：平面NFET器件，平面PFET器件和FinFET器件。 沟槽隔离围绕平面NFET器件，并且平面PFET器件穿透SOI并邻接绝缘体。 三种不同类型的器件中的每一种都包含高k栅极电介质层和中间间隙栅极金属层，每个包含相同的高k材料和相同的中间间隙金属。 三种不同类型的设备中的每一种具有单独优化的阈值。 还公开了一种用于制造电路结构的方法，该方法包括为三种不同类型的器件分别定义SOI中的部分：对于平面NFET器件，用于平面PFET器件和FinFET器件。 该方法还包括共同沉积高k栅极电介质层和中间间隙栅极金属层，并且使用功函数修改层来单独调节各种器件的阈值。

公开(公告)号：US08084309B2

公开(公告)日：2011-12-27

申请号：US12542179

申请日：2009-08-17

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ghavam G. Shahidi

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L21/84 ,  H01L21/823814 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

摘要： A method of fabricating an electronic structure is provided that includes forming a first conductivity doped first semiconductor material on the SOI semiconductor layer of a substrate. The SOI semiconductor layer has a thickness of less than 10 nm. The first conductivity in-situ doped first semiconductor material is removed from a first portion of the SOI semiconductor layer, wherein a remaining portion of the first conductivity in-situ doped first semiconductor material is present on a second portion of SOI semiconductor layer. A second conductivity in-situ doped second semiconductor material is formed on the first portion of the SOI semiconductor layer, wherein a mask prohibits the second conductivity in-situ doped semiconductor material from being formed on the second portion of the SOI semiconductor layer. The dopants from the first and second conductivity in-situ doped semiconductor materials are diffused into the first semiconductor layer to form dopant regions.

摘要翻译： 提供一种制造电子结构的方法，其包括在衬底的SOI半导体层上形成第一导电掺杂的第一半导体材料。 SOI半导体层的厚度小于10nm。 第一导电性原位掺杂的第一半导体材料从SOI半导体层的第一部分去除，其中第一导电性原位掺杂的第一半导体材料的剩余部分存在于SOI半导体层的第二部分上。 第二导电性原位掺杂的第二半导体材料形成在SOI半导体层的第一部分上，其中掩模禁止在SOI半导体层的第二部分上形成第二导电性原位掺杂半导体材料。 来自第一和第二导电性原位掺杂半导体材料的掺杂剂扩散到第一半导体层中以形成掺杂区域。