Packet transmission using scheduled prefetching

    公开(公告)号:US11388263B2

    公开(公告)日:2022-07-12

    申请号:US17067690

    申请日:2020-10-11

    Abstract: A Network-Connected Device (NCD) includes a network interface, a host interface, an NCD memory and an NCD processor. The network interface is configured for communicating over a network. The host interface is configured for communicating with a host. The NCD memory is configured to buffer packet information that originates from the host and pertains to a packet to be transmitted to the network at a specified transmission time. The NCD processor is configured to process the buffered packet information before the specified transmission time, and to transmit the packet to the network at the specified time. Processing of the packet information and transmission of the packet are decoupled from buffering of the packet information.

    Software-controlled clock synchronization of network devices

    公开(公告)号:US20220191275A1

    公开(公告)日:2022-06-16

    申请号:US17120313

    申请日:2020-12-14

    Abstract: A synchronized communication system includes a plurality of network communication devices, one of which is designated as a root device and the others designated as slave devices. Each network communication device includes one or more ports and communications circuitry, which processes the communication signals received by the one or more ports so as to recover a respective remote clock from each of the signals. A synchronization circuit is integrated in the root device and provides a root clock signal, which is conveyed by clock links to the slave devices. A host processor selects one of the ports of one of the network communication devices to serve as a master port, finds a clock differential between the root clock signal and the respective remote clock recovered from the master port, and outputs, responsively to the clock differential, a control signal causing the synchronization circuit to adjust the root clock signal.

    Packet Transmission Using Scheduled Prefetching

    公开(公告)号:US20220116473A1

    公开(公告)日:2022-04-14

    申请号:US17067690

    申请日:2020-10-11

    Abstract: A Network-Connected Device (NCD) includes a network interface, a host interface, an NCD memory and an NCD processor. The network interface is configured for communicating over a network. The host interface is configured for communicating with a host. The NCD memory is configured to buffer packet information that originates from the host and pertains to a packet to be transmitted to the network at a specified transmission time. The NCD processor is configured to process the buffered packet information before the specified transmission time, and to transmit the packet to the network at the specified time. Processing of the packet information and transmission of the packet are decoupled from buffering of the packet information.

    Regrouping of video data in host memory

    公开(公告)号:US20220095007A1

    公开(公告)日:2022-03-24

    申请号:US17542426

    申请日:2021-12-05

    Abstract: Apparatus for data communications includes a host interface, which is configured to be connected to a bus of a host computer having a processor and a memory. Processing circuitry, which is coupled to the host interface, is configured to receive video data with respect to a sequence of pixels, the video data including data words of more than eight bits per pixel for at least one pixel component of the pixels, and to write the video data, via the host interface, to at least one buffer in the memory while justifying the video data in the memory so that the successive pixels in the sequence are byte-aligned in the at least one buffer.

    Clock synchronization using digitally controlled oscillator

    公开(公告)号:US20250055667A1

    公开(公告)日:2025-02-13

    申请号:US18420822

    申请日:2024-01-24

    Abstract: In one embodiment, a system, includes a digitally controlled oscillator (DCO) to generate a local clock signal having a local clock frequency, and a hardware clock to maintain a value indicative of a local clock time advancing at a frequency proportional to the local clock frequency of the local clock signal generated by the DCO, and clock synchronization circuitry to receive from a device an indication of a remote clock time, generate a digital control command to at least partially correct for a difference between the remote clock time and the local clock time, and provide the digital control command to the DCO, wherein the DCO is to adjust the local clock frequency responsively to the digital control command.

    INTELLIGENT EXPOSURE OF HARDWARE LATENCY STATISTICS WITHIN AN ELECTRONIC DEVICE OR SYSTEM

    公开(公告)号:US20250036503A1

    公开(公告)日:2025-01-30

    申请号:US18916370

    申请日:2024-10-15

    Abstract: A method includes presenting, by a processing device, in a user interface of a display device, a set of menu items associated with a plurality of criteria and detecting one or more input signals from one or more selections of the set of menu items. The method includes creating a command that includes one or more criteria corresponding to selected options of the plurality of criteria derived from the one or more input signals. The method includes sending, by the processing device, the command to a network adapter device to trigger a polling operation to be performed that causes internal logic of the network adapter device to sample event data associated with a latency of data packets sent by a hardware process that is specific to the one or more criteria.

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