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公开(公告)号：US12224950B2
公开(公告)日：2025-02-11
申请号：US17979018
申请日：2022-11-02
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Gal Yefet , Daniel Marcovitch , Roee Moyal , Gil Bloch , Ariel Shahar , Yossef Itigin
IPC: G06F15/16 , H04L47/62 , H04L47/625 , H04L47/6275
Abstract: In one embodiment, a system includes a memory to store a work queue including work queue entry slots, a processing device to write work queue entries to the work queue in a consecutive and cyclic manner, and a network device including a network interface to share packet over a network, and packet processing circuitry to read the work queue entries from the work queue in a consecutive and cyclic manner, the work queue entries indicating work to be performed associated with the packets, dequeue respective ones of the work queue entries read from the work queue responsively to reading the respective work queue entries from the work queue, add the work queue entries to an execution database used to track execution of the work queue entries, and execute the work queue entries in the execution database.
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公开(公告)号：US20240143539A1
公开(公告)日：2024-05-02
申请号：US17977894
申请日：2022-10-31
Applicant: Mellanox Technologies, Ltd.
Inventor： Daniel Marcovitch , Richard Graham
IPC: G06F15/173 , G06F13/32
CPC classification number: G06F15/17331 , G06F13/32
Abstract: Disclosed are apparatuses, systems, and techniques that improve efficiency and decrease latency of remote direct memory access (RDMA) operations. The techniques include but are not limited to unified RDMA operations that are recognizable by various communicating devices, such as network controllers and target memory devices, as requests to establish, set, and/or update arrival indicators in the target memory devices responsive to arrival of one or more portions of the data being communicated.
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公开(公告)号：US20240098034A1
公开(公告)日：2024-03-21
申请号：US18524010
申请日：2023-11-30
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Yamin Friedman , Daniel Marcovitch , Gil Levy
Abstract: In one embodiment, a communication apparatus, including a network interface configured to receive over a network a sequence of data packets of a network flow having a defined packet order, wherein the network interface is configured to receive an out-of-order data packet instead of multiple missing data packets according to the defined packet order, a timer, and packet processing circuitry configured to activate the timer responsively to receiving the out-of-order data packet, and set the time period over which the timer is activated responsively to a quantity of the multiple missing data packets.
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公开(公告)号：US20240012773A1
公开(公告)日：2024-01-11
申请号：US17858102
申请日：2022-07-06
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Daniel Marcovitch , Gil Bloch , Richard Graham , Yossef Itigin , Ortal Ben Moshe , Roman Nudelman
IPC: G06F13/28
CPC classification number: G06F13/28 , G06F2213/28
Abstract: A Direct Memory Access (DMA) device includes an interface and a DMA engine. The interface is configured to communicate with a first memory and with a second memory. The DMA engine is configured to (i) receive a request to transfer data between the first memory and the second memory in accordance with a pattern of offsets to be accessed in the first memory or in the second memory, and (ii) transfer the data in accordance with the request.
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公开(公告)号：US11388263B2
公开(公告)日：2022-07-12
申请号：US17067690
申请日：2020-10-11
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Dotan David Levi , Daniel Marcovitch , Lior Narkis , Avi Urman
IPC: H04L49/90 , H04L67/5681 , H04W72/12
Abstract: A Network-Connected Device (NCD) includes a network interface, a host interface, an NCD memory and an NCD processor. The network interface is configured for communicating over a network. The host interface is configured for communicating with a host. The NCD memory is configured to buffer packet information that originates from the host and pertains to a packet to be transmitted to the network at a specified transmission time. The NCD processor is configured to process the buffered packet information before the specified transmission time, and to transmit the packet to the network at the specified time. Processing of the packet information and transmission of the packet are decoupled from buffering of the packet information.
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Patent Agency Ranking
公开(公告)号：US20220188147A1
公开(公告)日：2022-06-16
申请号：US17120321
申请日：2020-12-14
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Roman Nudelman , Gil Bloch , Daniel Marcovitch
Abstract: A network device includes a network interface, a host interface and processing circuitry. The network interface is configured to connect to a communication network. The host interface is configured to connect to a host including a processor. The processing circuitry is configured to receive from the processor, via the host interface, a notification specifying an operation for execution by the network device, the operation including (i) multiple tasks that are executable by the network device, and (ii) execution dependencies among the tasks in response to the notification, the processing circuitry is configured to determine a schedule for executing the tasks, the schedule complying with the execution dependencies, and to execute the operation by executing the tasks of the operation is accordance with the schedule.
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公开(公告)号：US20220116473A1
公开(公告)日：2022-04-14
申请号：US17067690
申请日：2020-10-11
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Dotan David Levi , Daniel Marcovitch , Lior Narkis , Avi Urman
IPC: H04L29/08
Abstract: A Network-Connected Device (NCD) includes a network interface, a host interface, an NCD memory and an NCD processor. The network interface is configured for communicating over a network. The host interface is configured for communicating with a host. The NCD memory is configured to buffer packet information that originates from the host and pertains to a packet to be transmitted to the network at a specified transmission time. The NCD processor is configured to process the buffered packet information before the specified transmission time, and to transmit the packet to the network at the specified time. Processing of the packet information and transmission of the packet are decoupled from buffering of the packet information.
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公开(公告)号：US12137141B2
公开(公告)日：2024-11-05
申请号：US17858097
申请日：2022-07-06
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Daniel Marcovitch , Gil Bloch , Richard Graham , Yossef Itigin , Ortal Ben Moshe , Roman Nudelman
IPC: H04L12/70 , H04L41/0806 , H04L67/1097 , H04L67/12 , H04W48/08
Abstract: A network device includes a first interface, a second interface and circuitry. The first interface is configured to communicate at least with a first memory. The second interface is configured to communicate over a network with a peer network device coupled to a second memory. The circuitry is configured to (i) receive a request to transfer data over the network between the first memory and the second memory in accordance with a pattern of offsets to be accessed in the first memory or in the second memory, and (ii) transfer the data in accordance with the request.
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公开(公告)号：US12135662B2
公开(公告)日：2024-11-05
申请号：US17858102
申请日：2022-07-06
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Daniel Marcovitch , Gil Bloch , Richard Graham , Yossef Itigin , Ortal Ben Moshe , Roman Nudelman
IPC: G06F13/28
Abstract: A Direct Memory Access (DMA) device includes an interface and a DMA engine. The interface is configured to communicate with a first memory and with a second memory. The DMA engine is configured to (i) receive a request to transfer data between the first memory and the second memory in accordance with a pattern of offsets to be accessed in the first memory or in the second memory, and (ii) transfer the data in accordance with the request.
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公开(公告)号：US20240340197A1
公开(公告)日：2024-10-10
申请号：US18744636
申请日：2024-06-16
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Daniel Marcovitch , Idan Burstein , Liran Liss , Hillel Chapman , Dror Goldenberg , Michael Kagan , Aviad Yehezkel , Peter Paneah
IPC: H04L12/46 , G06F13/40 , G06F13/42 , G06F15/173
CPC classification number: H04L12/4625 , G06F13/4027 , G06F13/4208 , G06F15/17331 , H04L12/4633 , G06F2213/0026
Abstract: A cross-network bridging apparatus includes a bus interface and bridging circuitry. The bus interface is configured for connecting to a system bus. The bridging circuitry is configured to translate between (i) system-bus transactions that are exchanged between one or more local devices that are coupled to the system bus and served by the system bus and one or more remote processors located across a network from the apparatus, and (ii) data units that convey the system-bus transactions, for transmitting and receiving as network packets over the network to and from the remote processors.
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