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公开(公告)号:US11594272B2
公开(公告)日:2023-02-28
申请号:US17409608
申请日:2021-08-23
Applicant: Micron Technology, Inc.
Inventor: Huy T. Vo , Adam S. El-Mansouri , Suryanarayana B. Tatapudi , John D. Porter
IPC: G11C11/22
Abstract: Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a first switching component may selectively couple a sense component with the memory cell based on a logic state stored on the memory cell to transfer a charge between the memory cell and the sense component. A second switching component, which may be coupled with the first switching component, may down convert a voltage associated with the charge to another voltage that is within an operation voltage of the sense component. The sense component may operate at a lower voltage than a voltage at which the memory cell operates to reduce power consumption in some cases.
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公开(公告)号:US11282560B2
公开(公告)日:2022-03-22
申请号:US17208433
申请日:2021-03-22
Applicant: Micron Technology, Inc.
Inventor: Victor Wong , Sihong Kim , Hiroshi Akamatsu , Daniele Vimercati , John D. Porter
Abstract: Methods, systems, and devices for temperature-based access timing for a memory device are described. In some memory devices, accessing memory cells may be associated with different operations that are variously dependent on a temperature of the memory device. For example, some operations associated with accessing a memory cell may have a longer duration and others a shorter duration depending on the temperature of the memory device. In accordance with examples as disclosed herein, a memory device may be configured for performing some portions of an access operation according to a duration that is proportional to a temperature of the memory device, and performing other portions of the access operation according to a duration that is inversely proportional to a temperature of the memory device.
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公开(公告)号:US20210217459A1
公开(公告)日:2021-07-15
申请号:US17161204
申请日:2021-01-28
Applicant: MICRON TECHNOLOGY, INC.
Inventor: Dean D. Gans , John D. Porter
IPC: G11C11/4076 , G11C11/4074 , G06F3/06 , G06F13/16
Abstract: Apparatuses and methods for input receiver circuits and receiver masks for electronic memory are disclosed. Embodiments of the disclosure include memory receiver masks having shapes other than rectangular shapes. For example, a receiver mask according to some embodiments of the disclosure may have a hexagonal shape. Other shapes of receiver masks may also be included in other embodiments of the disclosure. Circuits, timing, and operating parameters for achieving non-rectangular and various shapes of receiver mask are described.
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公开(公告)号:US20190333562A1
公开(公告)日:2019-10-31
申请号:US15962938
申请日:2018-04-25
Applicant: Micron Technology, Inc.
Inventor: Huy T. Vo , Adam S. El-Mansouri , Suryanarayana B. Tatapudi , John D. Porter
IPC: G11C11/22
Abstract: Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a first switching component may selectively couple a sense component with the memory cell based on a logic state stored on the memory cell to transfer a charge between the memory cell and the sense component. A second switching component, which may be coupled with the first switching component, may down convert a voltage associated with the charge to another voltage that is within an operation voltage of the sense component. The sense component may operate at a lower voltage than a voltage at which the memory cell operates to reduce power consumption in some cases.
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公开(公告)号:US20190267056A1
公开(公告)日:2019-08-29
申请号:US16274992
申请日:2019-02-13
Applicant: MICRON TECHNOLOGY, INC.
Inventor: Hyun Yoo Lee , Kang-Yong Kim , John D. Porter
IPC: G11C7/22 , H03K5/156 , G11C11/4076 , G11C8/18
Abstract: Apparatuses and methods for duty cycle distortion correction of clocks are disclosed. An example apparatus includes a clock circuit configured to receive complementary input clocks and a control signal and to provide multiphase clocks responsive to complementary input clocks. The clock circuit is further configured to be in a first mode or second mode controlled by the control signal and configured to provide the multiphase clocks having greater duty cycle distortion in a first mode than in a second mode.
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公开(公告)号:US10373660B1
公开(公告)日:2019-08-06
申请号:US16274992
申请日:2019-02-13
Applicant: MICRON TECHNOLOGY, INC.
Inventor: Hyun Yoo Lee , Kang-Yong Kim , John D. Porter
IPC: G11C8/16 , G11C7/22 , G11C8/18 , G11C11/4076 , H03K5/156
Abstract: Apparatuses and methods for duty cycle distortion correction of clocks are disclosed. An example apparatus includes a clock circuit configured to receive complementary input clocks and a control signal and to provide multiphase clocks responsive to complementary input clocks. The clock circuit is further configured to be in a first mode or second mode controlled by the control signal and configured to provide the multiphase clocks having greater duty cycle distortion in a first mode than in a second mode.
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公开(公告)号:US10249354B1
公开(公告)日:2019-04-02
申请号:US15903934
申请日:2018-02-23
Applicant: Micron Technology, Inc.
Inventor: Hyun Yoo Lee , Kang-Yong Kim , John D. Porter
IPC: G11C8/18 , G11C7/22 , G11C11/4076 , H03K5/156
Abstract: Apparatuses and methods for duty cycle distortion correction of clocks are disclosed. An example apparatus includes a clock circuit configured to receive complementary input clocks and a control signal and to provide multiphase clocks responsive to complementary input clocks. The clock circuit is further configured to be in a first mode or second mode controlled by the control signal and configured to provide the multiphase clocks having greater duty cycle distortion in a first mode than in a second mode.
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58.
公开(公告)号:US20190080743A1
公开(公告)日:2019-03-14
申请号:US16190504
申请日:2018-11-14
Applicant: MICRON TECHNOLOGY, INC.
Inventor: Hyun Yoo Lee , Kang-Yong Kim , John D. Porter
IPC: G11C11/4076 , G11C7/10 , G11C11/4096 , G11C7/22 , G11C11/4074 , G11C11/4093 , G11C11/4091
Abstract: Apparatuses and methods for configurable command and data input circuits for semiconductor memories are described. Example apparatuses include input signal blocks, clock blocking circuits, data input blocks, driver circuits, and data receiver circuits.
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公开(公告)号:US20180190342A1
公开(公告)日:2018-07-05
申请号:US15910867
申请日:2018-03-02
Applicant: Micron Technology, Inc.
Inventor: Donald M. Morgan , John D. Porter
IPC: G11C11/406 , G11C11/408
CPC classification number: G11C11/40615 , G11C11/40603 , G11C11/40618 , G11C11/408
Abstract: Various embodiments comprise methods and apparatuses for selecting a randomly-chosen seed row from among a stream of available data in a memory system. A refresh operation is then performed on at least one selected row of memory in the memory system based on the randomly-chosen seed row. Additional apparatuses and methods are described.
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