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    SYSTEM AND METHOD FOR PROCESSING SIGNALS IN HIGH SPEED DRAM
    1.
    发明申请
    SYSTEM AND METHOD FOR PROCESSING SIGNALS IN HIGH SPEED DRAM 有权
    用于在高速DRAM中处理信号的系统和方法

    公开(公告)号：US20130242685A1

    公开(公告)日：2013-09-19

    申请号：US13886096

    申请日：2013-05-02

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Ben Ba ,  Victor Wong

    IPC: G11C8/08

    CPC classification number: G11C8/08 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C8/12 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4087

    Abstract: The embodiments described herein provide memory devices. In one embodiment, a memory device includes bank control logic configured to generate a modified bank address signal and an active driver configured to provide a bank activate signal, receive an activate command signal, execute an activate command of the activate command signal at each one of a group of clock cycles, in which each one of the group of clock cycles is greater than one clock cycle, and receive the modified bank address signal, in which the modified bank address signal is high for at least a portion of each one of the group of clock cycles and the at least a portion of each one of the group of clock cycles is greater than one clock cycle.

    Abstract translation: 这里描述的实施例提供存储器件。 在一个实施例中，存储器设备包括：组控制逻辑，其被配置为生成修改的存储体地址信号;以及主动驱动器，其被配置为提供存储体激活信号，接收激活命令信号，执行激活命令信号的激活命令 一组时钟周期，其中该组时钟周期中的每一个大于一个时钟周期，并且接收修改的库地址信号，其中修改的库地址信号对于每个时钟周期的每一个的至少一部分 一组时钟周期，并且该组时钟周期中的每一个的至少一部分大于一个时钟周期。

    TEMPERATURE-BASED ACCESS TIMING FOR A MEMORY DEVICE
    2.
    发明申请
    TEMPERATURE-BASED ACCESS TIMING FOR A MEMORY DEVICE 有权

    公开(公告)号：US20210304806A1

    公开(公告)日：2021-09-30

    申请号：US17208433

    申请日：2021-03-22

    Applicant: Micron Technology, Inc.

    Inventor： Victor Wong ,  Sihong Kim ,  Hiroshi Akamatsu ,  Daniele Vimercati ,  John D. Porter

    IPC: G11C11/22

    Abstract: Methods, systems, and devices for temperature-based access timing for a memory device are described. In some memory devices, accessing memory cells may be associated with different operations that are variously dependent on a temperature of the memory device. For example, some operations associated with accessing a memory cell may have a longer duration and others a shorter duration depending on the temperature of the memory device. In accordance with examples as disclosed herein, a memory device may be configured for performing some portions of an access operation according to a duration that is proportional to a temperature of the memory device, and performing other portions of the access operation according to a duration that is inversely proportional to a temperature of the memory device.

    APPARATUSES AND METHODS FOR IMPLEMENTING MASKED WRITE COMMANDS
    4.
    发明申请
    APPARATUSES AND METHODS FOR IMPLEMENTING MASKED WRITE COMMANDS 有权
    实施掩蔽写作命令的手段和方法

    公开(公告)号：US20150302907A1

    公开(公告)日：2015-10-22

    申请号：US14254378

    申请日：2014-04-16

    Applicant: Micron Technology, Inc.

    Inventor： Mark K. Hadrick ,  Jeffrey P. Wright ,  Victor Wong ,  Simon J. Lovett ,  Donald M. Morgan ,  William F. Jones ,  Sujeet Ayyapureddi ,  Dean D. Gans ,  Jongtae Kwak

    IPC: G11C8/06 ,  G11C7/22

    CPC classification number: G11C7/22 ,  G11C7/1009 ,  G11C7/1042 ,  G11C8/12 ,  G11C2207/229

    Abstract: Apparatuses and methods for implementing masked write commands are disclosed herein. An example apparatus may include a memory bank, a local buffer circuit, and an address control circuit. The local buffer circuit may be associated with the memory bank. The address control circuit may be coupled to the memory bank and configured to receive a command and an address associated with the command. The address control circuit may include a global buffer circuit configured to store the address. The address control circuit may further be configured to delay the command using one of a plurality of command paths based, at least in part, on a write latency and to provide the address stored in the global buffer circuit to the local buffer circuit to be stored therein.

    Abstract translation: 本文公开了用于实现屏蔽写入命令的装置和方法。 示例性装置可以包括存储体，局部缓冲电路和地址控制电路。 本地缓冲电路可以与存储体相关联。 地址控制电路可以耦合到存储体并被配置为接收命令和与命令相关联的地址。 地址控制电路可以包括被配置为存储地址的全局缓冲电路。 地址控制电路还可以被配置为至少部分地基于写等待时间来延迟使用多个命令路径之一的命令，并且将存储在全局缓冲器电路中的地址提供给要存储的本地缓冲器电路 其中。

    Handling Faulty Usage-Based-Disturbance Data
    5.
    发明申请
    Handling Faulty Usage-Based-Disturbance Data 有权

    公开(公告)号：US20250130877A1

    公开(公告)日：2025-04-24

    申请号：US18790795

    申请日：2024-07-31

    Applicant: Micron Technology, Inc.

    Inventor： Yang Lu ,  Mark Kalei Hadrick ,  Kang-Yong Kim ,  Donald Morgan ,  Victor Wong

    IPC: G06F11/07

    Abstract: Apparatuses and techniques for handling faulty usage-based-disturbance data are described. In an example aspect, a memory device uses a report flag to indicate that an address of a row that corresponds to the faulty usage-based-disturbance data is logged at a global-bank level and is accessible by a host device. The report flag also enables the memory device to avoid reporting another error until the host device has cleared information associated with a previously-reported error. In another example aspect, the memory device temporarily prevents usage-based-disturbance mitigation from being performed based on the faulty usage-based-disturbance data. This means that if the faulty usage-based-disturbance data would otherwise trigger refreshing of one or more rows that are proximate to the row corresponding to the faulty usage-based-disturbance data, the memory device does not perform these refresh operations. This is beneficial by conserving resources for refreshing victim rows that are identified based on valid usage-based-disturbance data.

    Usage-Based-Disturbance Alert Signaling
    6.
    发明申请
    Usage-Based-Disturbance Alert Signaling 有权

    公开(公告)号：US20250094262A1

    公开(公告)日：2025-03-20

    申请号：US18787655

    申请日：2024-07-29

    Applicant: Micron Technology, Inc.

    Inventor： Yang Lu ,  Victor Wong ,  Donald Morgan

    IPC: G06F11/07

    Abstract: Apparatuses and techniques for implementing usage-based-disturbance alert signaling are described. The technology allows usage-based-disturbance (UBD) alerts to be externally communicated from a memory device without a dedicated external interface. Rather, UBD alerts are combined with memory error/alert signals and communicated on a shared alert-related interface. UBD tracking occurs at the memory bank level, with corresponding independent UBD alert signals. These signals are efficiently combined to generate an overall UBD alert. A temporary backoff signal is generated when an overall UBD alert is sent. The backoff signal ensures requisite external timing parameters are met while allowing the individual memory banks to generate persistent UBD alerts.

    ERROR CONTROL FOR MEMORY DEVICE
    7.
    发明申请
    ERROR CONTROL FOR MEMORY DEVICE 有权

    公开(公告)号：US20210383888A1

    公开(公告)日：2021-12-09

    申请号：US16895960

    申请日：2020-06-08

    Applicant: Micron Technology, Inc.

    Inventor： Nobuo Yamamoto ,  Donald Martin Morgan ,  Victor Wong ,  Jongtae Kwak

    IPC: G11C29/42 ,  G11C29/44 ,  G11C29/20 ,  G11C16/26 ,  G11C16/10

    Abstract: Methods, systems, and devices for error control for memory device are described. A memory device may be configured to perform memory management operations including error control operations. For example, a memory device may be configured to perform an error control operation on data stored in a first memory cell coupled with a source row of a memory array. The memory device may be configured to write the data to a second memory cell coupled with the target row of the memory array based on performing the error control operation on the data and determine whether the management operation is complete based at least in part on the first column address of the first memory cell. The memory device may also generate an output signal to perform the error control operation on a third memory cell coupled with the source row based on determining whether the management operation is complete.

    Temperature-based access timing for a memory device
    8.
    发明授权
    Temperature-based access timing for a memory device 有权

    公开(公告)号：US11282560B2

    公开(公告)日：2022-03-22

    申请号：US17208433

    申请日：2021-03-22

    Applicant: Micron Technology, Inc.

    Inventor： Victor Wong ,  Sihong Kim ,  Hiroshi Akamatsu ,  Daniele Vimercati ,  John D. Porter

    IPC: G11C7/04 ,  G11C11/22

    Abstract: Methods, systems, and devices for temperature-based access timing for a memory device are described. In some memory devices, accessing memory cells may be associated with different operations that are variously dependent on a temperature of the memory device. For example, some operations associated with accessing a memory cell may have a longer duration and others a shorter duration depending on the temperature of the memory device. In accordance with examples as disclosed herein, a memory device may be configured for performing some portions of an access operation according to a duration that is proportional to a temperature of the memory device, and performing other portions of the access operation according to a duration that is inversely proportional to a temperature of the memory device.

    Logging a Memory Address Associated with Faulty Usage-Based Disturbance Data
    10.
    发明申请
    Logging a Memory Address Associated with Faulty Usage-Based Disturbance Data 有权

    公开(公告)号：US20250131973A1

    公开(公告)日：2025-04-24

    申请号：US18790365

    申请日：2024-07-31

    Applicant: Micron Technology, Inc.

    Inventor： Yang Lu ,  Mark Kalei Hadrick ,  Kang-Yong Kim ,  Donald Morgan ,  Victor Wong

    IPC: G11C29/44 ,  G11C29/30 ,  G11C29/36

    Abstract: Apparatuses and techniques for logging a memory address associated with faulty usage-based disturbance data are described. In an example aspect, a memory device can detect, at a local-bank level, a fault associated with usage-based disturbance data. This detection enables the memory device to log a row address associated with the faulty usage-based disturbance data. To avoid increasing a complexity and/or a size of the memory device, some implementations of the memory device can perform the address logging at the multi-bank level with the assistance of an engine, such as a test engine. The memory device stores the logged address in at least one mode register to communicate the fault to a memory controller. With the logged address, the memory controller can initiate a repair procedure to fix the faulty usage-based disturbance data.

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